Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

High accuracy direct reading capacitance-to-voltage converter

Abstract: A relatively simple circuit for implementing a low-cost, low power, highly accurate capacitance-to-voltage converter by which to measure the unknown capacitance of a capacitor The circuit is characterized by the ability to eliminate error due to stray capacitance sources The circuit is implemented by a crystal controlled clock generator which produces multi-phase clock signals to control the operation of a pair of series connected field effect transistors and a buffer amplifier The field effect transistors are alternately switched on and off to periodically charge and discharge the capacitor under measurement between a source of reference potential and the inverting input terminal of a precision operational amplifier The output voltage of the operational amplifier tracks the capacitance of the capacitor under measurement, such that an accurate indication of its capacitance is obtained by merely reading the output of the operational amplifier

Linearized capacitance sensor system

Abstract: A capacitive sensing circuit and system includes a variable capacitance sensing element as an active element in a circuit to measure changes in capacitance of the sensing element. A switching network in alternate cycles energizes a capacitor to develop a charge which effectively linearizes the sensor's capacitance response. In a push-pull circuit with two active sensing elements, a multi-channel switching network energizes two fixed correction capacitors to provide third or higher order correction, significantly extending the effective scale of the sensor. In a preferred embodiment, a single feedback signal is applied to all capacitors in different switching cycles. Examples include weight and pressure sensing systems.

Structure and Dimension Effects on the Performance of Layered Triboelectric Nanogenerators in Contact-Separation Mode

Abstract: A triboelectric nanogenerator (TENG) is a potential solution for providing high output power by continuously harvesting ambient energy, which is expected to sustainably charge a battery for the new era—the era of the Internet of things and sensor networks. Generally, the existence of parasitic capacitance has been considered to be harmful in its output performance. Here, we systematically investigate the effects of structure and dimension of a TENG on its performance from the point view of parasitic capacitance by fabricating two types of layered TENGs with considering the dissimilarity of the two dielectric materials, symmetrical (ABBA) and alternate (ABAB) layered structure (SYM-TENG and ALT-TENG). Theoretical models of the two types of layered TENGs are proposed for illustrating their differences in parasitic capacitances and output characteristics. Larger parasitic capacitance enables the TENG to accommodate higher triboelectric charge density while reducing the internal impedance and maximum power de...

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

Abstract: An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ?m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates

Abstract: In this paper, a new domino circuit is proposed, which has a lower leakage and higher noise immunity without dramatic speed degradation for wide fan-in gates. The technique which is utilized in this paper is based on comparison of mirrored current of the pull-up network with its worst case leakage current. The proposed circuit technique decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates to implement fast and robust circuits. Thus, the contention current and consequently power consumption and delay are reduced. The leakage current is also decreased by exploiting the footer transistor in diode configuration, which results in increased noise immunity. Simulation results of wide fan-in gates designed using a 16-nm high-performance predictive technology model demonstrate 51% power reduction and at least 2.41t noise-immunity improvement at the same delay compared to the standard domino circuits for 64-bit OR gates.