Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

A CMOS Class-E Power Amplifier With Voltage Stress Relief and Enhanced Efficiency

Abstract: This paper proposes a class-E power amplifier (PA) with double-resonance circuit to reduce voltage stress on CMOS transistors. The voltage waveform applied to the CMOS transistor is shaped by harmonic control and the transistors are relieved from breakdowns. A negative capacitance is also implemented for efficiency enhancement, compensating for surplus capacitance from parasitic components on the drain node. Thus, nominal class-E operation is restored and high efficiency is achieved. We present a cascode differential class-E RF PA that is fabricated using a 0.13-? m CMOS technology that delivers 31.5-dBm output power with 54% drain efficiency and 51% power-added efficiency at 1.8 GHz.

Electrical and Dielectric Properties of Wet Bone as a Function of Frequency

Abstract: The electrical and dielectric properties of wet, bovine, compact bone were determined in three orthogonal planes, using a differential technique, for a frequency range of 1 kHz-l MHz. For axial specimens, at 10 kHz, the specific resistance, specific capacitance, and specific impedance were 16.6 k?/cm, 60.9 pF. cm-1 and 16.59/?3.65°k?·cm, respectively. Similarly, the dielectric properties, namely the relative dielectric constant, relative dielectric loss factor and dielectric dissipation factor were 688, 10.8 ×103, and 15.7, respectively. The electrical properties were found to be highly dependent on the frequency and the moisture content of bone. The bone was also found to be highly anisotropic in its electrical behavior, the impedance being lowest in the axial direction. It is shown that the differential method provides an accurate means of measuring the electrical properties of bone, avoiding stray capacitance errors.

Design of Inductor Winding Capacitance Cancellation for EMI Suppression

Abstract: In this paper, the parasitics in both DM and CM inductors are first discussed. The methods for both DM and CM inductor winding capacitance cancellation are then proposed. Prototypes are designed and tested, using network analyzer. Finally, the prototypes are applied to practical power converters and EMI is measured. Both small signal measurement and practical EMI measurement prove that the proposed methods can efficiently reduce the effects of winding capacitance and therefore improve the inductor's filtering performance.

Measurements and analyses of substrate noise waveform in mixed-signal IC environment

Abstract: A transition-controllable noise source is developed in a 0.1-/spl mu/m P-substrate N-well CMOS technology. This noise source can generate substrate noises with controlled transitions in size, interstage delay and direction for experimental studies on substrate noise properties in a mixed-signal integrated circuit environment. Substrate noise measurements of 100 ps, 100-/spl mu/s resolution are performed by indirect sensing that uses the threshold voltage shift in a latch comparator and by direct probing that uses a PMOS source follower. Measured waveforms indicate that peaks reflecting logic transition frequencies have a time constant that is more than ten times larger than the switching time. Analyses with equivalent circuits confirm that charge transfer between the entire parasitic capacitance in digital circuits and an external supply through parasitic impedance to supply/return paths dominates the process, and the resultant return bounce appears as the substrate noise.

Two-Capacitor Transformer Winding Capacitance Models for Common-Mode EMI Noise Analysis in Isolated DC–DC Converters

Abstract: For isolated dc–dc power converters, the interwinding parasitic capacitance of the transformer is usually one of the main paths for common-mode (CM) noise. In order to simplify the CM noise analysis, this paper proposes a two-capacitor transformer winding capacitance model. The model is derived based on general conditions so it can be applied to different isolated converter topologies. A measurement technique is also proposed to obtain the lumped capacitance for the model. The CM noise models of several isolated converter topologies are analyzed with the proposed two-capacitor transformer winding capacitance model to achieve simplicity. Finally, the proposed transformer winding capacitance model and measurement technique are verified by simulations and experiments.