Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Effects on DC SQUID characteristics of damping of input coil resonances

Abstract: The possibility of improving dc SQUID performance by damping the input circuit resonances caused by parasitic capacitances is studied experimentally A high-quality dc SQUID was coupled to a first-order axial gradiometer built for neuromagnetic research, and a resistor-capacitor shunt was connected in parallel with the input coil of the SQUID Ten different RC shunts were studied with the SQUID operating in a flux-locked loop, carefully shielded against external disturbances It was found that increasing the shunt resistance resulted in smoother flux-voltage characteristics and smaller noise At best, the minimum obtainable equivalent flux noise level was one-fourth that for the unshunted SQUID The noise level is a function of the shunt resistance R/sub s/ only, except for shunt capacitance values bringing the low-frequency resonance of the input coil close to the flux modulation frequency At a constant bias current level, where the amplitude of the flux-voltage characteristics is at maximum, the equivalent flux noise varies as R/sub s//sup -07/ The results agree reasonably well with recently published predictions based on numerical simulations where the whole input circuit with parasitic capacitances was taken into account

Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics

Abstract: In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters.

Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling

Abstract: This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time Furthermore, an optimal repeater insertion scheme for distributed RLC interconnects is also presented using a novel performance optimization methodology Additionally, the impact of line inductance on interconnect performance has been analyzed in detail with particular regards to technology scaling based on the International Technology Roadmap for Semiconductors (ITRS) Contrary to conventional wisdom, it is shown that the effect of line inductance on optimized interconnect performance will actually diminish for scaled global interconnects

High frequency and high resolution capacitance measuring circuit for process tomography

Abstract: A stray-immune AC capacitance measuring circuit has been developed for electrical capacitance tomography. For this application a high excitation frequency is essential to achieve high sensitivity and fast data collection rates, and also to reduce the effect of any conductive component in parallel with the measured capacitance. A high excitation frequency has been made possible by using some novel methods: (a) a high frequency digital signal generator; (b) parameter-optimised AC amplifiers and (c) a phase-sensitive demodulator utilising CMOS switches. With a 500 kHz excitation signal the circuit has good linearity and stability, and a resolution of 0.035 fF.

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

Abstract: An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.