Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies

Abstract: A method for reducing the parasitic capacitance and capacitive coupling of nodes (106) in a dielectrically isolated integrated circuit (100) using layout changes. A separate area of floating silicon (110) is created adjacent two or more dielectrically isolated nodes (106). The two or more nodes (106) are chosen that "slew together" (i.e., nodes that are required to change by the same voltage at the same time). The area of floating silicon (110) is created by placing an additional trench (112) around both of the dielectrically isolated nodes (106).

A Sub-μA fast-settling current-programmed pixel circuit for AMOLED displays

Abstract: Current-programmed active matrix organic light emitting diode (AMOLED) displays have been valued for their immunity to spatial mismatch, differential aging, and temperature variation. However, the long settling time particularly at small current levels and large parasitic capacitance can be a constraint. This paper presents a new current-programmed pixel circuit that improves the settling time while preserving the stability of current programming. The pixel circuit was fabricated in amorphous silicon technology. The settling time of the new pixel circuit can be as low as 20 mus whereas the settling time of conventional current-programmed pixel is more than 2 ms.

Measurement-Based Method to Characterize Parasitic Parameters of the Integrated Power Electronics Modules

Abstract: A measurement-based method for extracting the parasitic parameters of active power electronics modules (IPEMs) is proposed. Parasitic inductances and capacitances inside the IPEM can all be extracted using this method without destroying the structure. The linearized model is derived from impedance measurement and it is valid from low frequency to frequencies as high as 100 MHz. Extracted parameters are compared to those from commercial software and the results are in good agreement. A parallel resonance method is proposed for the characterization of common-mode capacitances

Wide-band single-ended to differential converter in CMOS technology

Abstract: A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

Electrical through-wafer interconnects with sub-picofarad parasitic capacitance [MEMS packaging]

Abstract: This paper presents a technology for high density and low parasitic capacitance electrical through-wafer interconnects to an array of capacitive micromachined ultrasonic transducers (CMUTs) on a silicon wafer. Vertical wafer feedthroughs (interconnects) connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the wafer. A 20 to 1 high aspect ratio 400 /spl mu/m long and 20 /spl mu/m diameter interconnect is achieved by using deep reactive ion etching (DRIE). Reduction of the parasitic capacitance of the polysilicon pads to the substrate can be achieved by using reversed-biased pn-junction diodes operating in the depletion region. A parasitic capacitance of 0.3 pF has been achieved by this means. This three-dimensional architecture allows for elegant packaging through simple flip-chip bonding of the chip's back side to a printed circuit board (PCB) or a signal processing wafer.