Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Planar Transformers With Near-Zero Common-Mode Noise for Flyback and Forward Converters

Abstract: Flyback and forward converters are two commonly used topologies for isolated low-power applications. These converters are simple and cost effective and provide galvanic isolation, which make them desirable for low-power levels. In order to enhance the performance of these converters, planar transformers (PTs) can be used that feature lower height, considerably lower leakage inductance, excellent thermal characteristics, and repeatability. Selecting a proper winding arrangement for a PT is a significant challenge, in particular given the large capacitances involved in flat structures. While interleaved structures significantly reduce the ac resistance and leakage inductance of PTs, they also lead to very large interwinding capacitance, which produces significant levels of undesired common-mode (CM) noise that causes EMI problems. Reducing interwinding capacitance by using noninterleaved structures is not an ideal solution to the CM noise problem because of its side effects. Instead, this paper tackles the problem by proposing the concept of paired layers. According to this concept, there are layers in the primary and secondary sides that have the same $dv/dt$ , and therefore, their overlapping does not generate CM noise. These layers can be used to design highly interleaved structures that not only have very low ac resistance and leakage inductance, but also generate almost zero CM noise, although they may have a very large interwinding capacitance. In addition, a detailed parasitic capacitance model of PTs is proposed, which analytically validates the proposed concept and method. The experimental results show that the proposed PTs not only have very low ac resistance and leakage inductance, but also generate extremely low levels of CM noise. Considering that the proposed PT has interwinding capacitance equal to $\text{700 pF}$ , it is very interesting to see that it generates significantly less CM noise than does a traditional wire-wound transformer that has only $\text{10-pF}$ parasitic capacitance. Therefore, the proposed method gives designers the opportunity to minimize ac resistance and leakage inductance by using highly interleaved structures, without having to worry about CM noise caused by large interwinding capacitance.

A 156-Mb/s CMOS optical receiver for burst-mode transmission

Abstract: In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-/spl mu/m CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module.

A Compact, Low Input Capacitance Neural Recording Amplifier

Abstract: Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm2. It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated.

Dynamic RAM and information processing system using the same

Abstract: A dynamic RAM is provided using a sense amplifier compensating for the disparities of characteristics for paired MOSFET's. With this arrangement parasitic capacitance of the bit lines can be increased to be at least 20 times the capacitance of the memory cells. Each bit line is bisected by a switch MOSFET and is disconnected thereby as needed. A plurality of sets of memory arrays are furnished, each including a switch MOSFET for interconnecting common source lines to which the sense amplifier is connected. This permits recycling of the charges of the common source lines.

Low-Noise Amplifier Design With Dual Reactive Feedback for Broadband Simultaneous Noise and Impedance Matching

Abstract: The simultaneous noise and impedance matching (SNIM) condition for a common-source amplifier is analyzed Transistor noise parameters are derived based on the more complete hybrid-? model, and the dominant factors jeopardizing SNIM are identified Strategies for narrowband and broadband SNIM (BSNIM) are derived accordingly A dual reactive feedback circuit along with an LC-ladder matching network is proposed to achieve the BSNIM It includes a capacitive and an inductive feedback, where the former utilizes the transistor parasitic gate-to-drain capacitance and the latter is formed by transformer coupling This circuit topology has been validated in 018- and 013- ?m CMOS technologies for a 3-11-GHz ultra-wideband (UWB) and a 24-54-GHz multistandard application, respectively The 3-11-GHz UWB low-noise amplifier is detailed as a design example