Topic
Parasitic capacitance
About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.
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TL;DR: In this article, the absolute maximum voltage developed across an electrostatic actuator when driven by a current source has been calculated as well as an absolute minimum for the pull-in time for a drive using a /spl delta/-pulse of current and numerical assessment is given to show that for a nonzero parasitic capacitance, a realistic shape of the current pulse, or a finite value of the damping coefficient do not increase the maximum value of voltage developed beyond that limit.
Abstract: The absolute maximum value of the voltage developed across an electrostatic actuator when driven by a current source has been calculated as well as an absolute minimum for the pull-in time. These two results are calculated for a drive using a /spl delta/-pulse of current and numerical assessment is given to show that for a nonzero parasitic capacitance, a realistic shape of the current pulse, or a finite value of the damping coefficient do not increase the maximum value of the voltage developed beyond that limit and that the pull-in time is always larger than the analytical minimum. A scaled-up macromodel of an electrostatic actuator has been used to register voltage transients to validate the theoretical predictions.
69 citations
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30 Jun 2011TL;DR: In this article, a chemically-sensitive transistor device, such as an ISFET, is used to test the functionality of the transistor without exposing the device to liquids, and the parasitic capacitance of at least either the source or drain is exploited to bias the floating gate.
Abstract: The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.
69 citations
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TL;DR: In this paper, a quasi-resonant (QR) flyback dual-output LED driver with current-sharing transformer (CST) is analyzed thoroughly, and the theoretical analysis shows that the parasitic capacitance of CST and its magnetizing inductance have a significant effect on the output current deviation and diode's voltage stress.
Abstract: In this paper, a quasi-resonant (QR) flyback dual-output LED driver with current-sharing transformer (CST) is analyzed thoroughly. Although the CST is utilized to balance the currents in two LED strings, from the theoretical analysis, it shows that the parasitic capacitance of CST and its magnetizing inductance have a significant effect on the output current deviation and diode's voltage stress. In order to achieve the optimal current sharing ability between two outputs with minimum auxiliary components, a design guideline for the CST in QR flyback is proposed according to the theoretical analysis. A 100-W dual-output dc-dc prototype is built up to verify the theoretical analysis.
69 citations
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TL;DR: In this article, a pixel circuit corresponding to one pixel includes a reset transistor for resetting a cathode of the photo-electric conversion element to initial voltage, an amplifying transistor for converting electric charges accumulated in the photoelectric conversion elements to voltage, and a row selection transistor for selecting signals output from pixel areas arranged in a row direction.
Abstract: A CMOS image sensor that reduces kTC noise in a wide band. A pixel circuit corresponding to one pixel includes a photoelectric conversion element for carrying out the photoelectric conversion of incident light, a reset transistor for resetting a cathode of the photoelectric conversion element to initial voltage, an amplifying transistor for converting electric charges accumulated in the photoelectric conversion element to voltage, and a row selection transistor for selecting signals output from pixel areas arranged in a row direction. A voltage control circuit controls the potential of a gate of the reset transistor during a period when the photoelectric conversion element is reset to change ON-state resistance of the reset transistor. By doing so, a cutoff frequency for a low-pass filter formed in the pixel circuit by ON-state resistance of the reset transistor and parasitic capacitance produced at the cathode on the photoelectric conversion element will be controlled.
69 citations
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25 Jun 1984TL;DR: The paper describes the decomposition algorithm, the extraction algorithms and discusses how they connect with the rest of EXCL, an automated circuit extraction program that transforms an IC layout into a circuit representation suitable for detailed circuit simulation.
Abstract: This paper describes EXCL, an automated circuit extraction program that transforms an IC layout into a circuit representation suitable for detailed circuit simulation. The program has built-in, general extraction algorithms capable of accurate computations of interconnection resistance, internodal capacitance, ground capacitance, and transistor sizes. However, where possible, the general algorithms are replaced with simple techniques, thereby improving execution speed. A basic component of the extractor is a procedure that decomposes regions into domains appropriate for specialized or simple algorithms. The paper describes the decomposition algorithm, the extraction algorithms and discusses how they connect with the rest of EXCL.
69 citations