Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Constant frequency, zero-voltage-switching converters with resonant switching bridge

Abstract: A novel, compact, converter structure utilizes a switching bridge configuration to provide a low voltage stress, constant frequency controlled converter whose switches and diodes all turn-on and turn-off with zero-voltage-switching. The novel converter configuration uses a full-bridge switching circuit comprising four diodes D1 -D4 and, in one embodiment, four active semiconductor switches S1 -S4. A resonant inductor Lr is connected across the bridge nodes a and b, and parasitic capacitance of the diodes and active switches S1 -S4 are incorporated in an L-C circuit. Connected in parallel with the bridge is a voltage source or sink, depending on the direction that power will flow; and connected to node a or b is a current source or sink, again depending upon the direction of power flow. The present invention stores sufficient energy in the resonant inductor Lr so that prior to each switch or diode commutation, charge present on the corresponding parasitic capacitance of that semiconductor may be removed by the current drawing action of the resonant inductor Lr. In this way, all diodes D1 -D4 and active switches S1 -S4 operate with zero-voltage-switching. The novel bridge configuration directs the power flow from the source to the load, while passively guaranteeing voltage limitation across each diode and switch, and providing volts-seconds balance for the resonant inductor Lr.

Humidity sensors using porous silicon layer with mesa structure

Abstract: A capacitance-type humidity sensor in which a porous silicon layer is used as a humidity-sensing material was developed This sensor was fabricated monolithically to be compatible with the typical IC process technology except for the formation of porous silicon layer As the sensor is made as a mesa structure, the correct measurement of capacitance is expected because it can remove the effect of the parasitic capacitance from the bottom layer and other junctions To do this, the sensor was fabricated using process steps such as the localized formation of porous silicon, oxidation of the porous silicon layer, and etching of the oxidized porous silicon layer From completed sensors, capacitance response was measured at a relative humidity of 25-95% at room temperature As a result, the measured capacitance showed an increase over 300% at the low frequency of 120 Hz, and showed little dependence on temperature between 10 and 40 °C

Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device

Abstract: A method for making DRAM devices having reduced parasitic capacitance between closely spaced capacitors is achieved. After forming FETs for the memory cells and bit lines having bit-line contacts, a planar insulating layer is formed having an etch-stop layer thereon. Contact openings are etched in the insulating layer and are filled with polysilicon to make contact to capacitor node contact plugs. A relatively thick insulating layer having a low dielectric constant (k) is deposited, and an array of recesses are etched over the node contact plugs for crown-shaped capacitors. A polysilicon layer and an interelectrode dielectric layer are formed in the array of recesses, and another polysilicon layer is patterned to complete the crown capacitors. The low-k insulator between adjacent capacitors reduces the parasitic capacitance and improves data retention of DRAM cells. Alternatively, higher density of memory cells can be formed without increasing parasitic capacitance.

Low capacitance interconnection

Abstract: A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.

Analysis of mesastable operation in RS CMOS flip-flops

Abstract: An analysis of metastable operation in CMOS RS flip-flops is presented. An analytical formula for the flip-flop resolving time constant was derived using Shichman-Hodges model for NMOS and PMOS transistors. This formula, as related to the transistor dimensions, fabrication process parameters, and parasitic capacitance, uses proper transistor sizing to attain minimum flip-flop failure rate due to metastable operation. CMOS n-well, p-well, and twin-well flip-flop performance predicted analytically is also approved by SPICE level one simulation of transistor models. Real-time oscilloscope displays of metastable operation for two different CMOS RS flip-flop circuits are demonstrated.