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Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.


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Proceedings Article
01 Jan 2002
TL;DR: Although the loading capacitance is omitted a very precise absolute oscillation frequency can be obtained as well as an excellent insensitivity to temperature variations thanks to the reduced parasitics of a deep-submicron technology.
Abstract: A crystal-based differential oscillator circuit offering simultaneously high stability and ultra-low power consumption is presented for timekeeping and demanding radio applications. The differential circuit structure -in contrast to that of the conventional 3-points- does not require any loading capacitance to be functional and the power consumption can thus be minimized. Although the loading capacitance is omitted a very precise absolute oscillation frequency can be obtained as well as an excellent insensitivity to temperature variations thanks to the reduced parasitics of a deep-submicron technology. The power consumption of a 12.8MHz quartz oscillator including an amplitude regulation mechanism is below 1 µA under a 1.8 to 0.6V supply voltage range.

61 citations

Patent
24 Mar 1995
TL;DR: In this article, a low-noise pulse is generated by a low pass filter and a pulse shaper, and the output signal is a signal which varies with the charging current through the capacitance voltage measured by a single transistor, and when the transistor is turned on, the charging voltage is diverted via the transistor, so that the capacitor voltage is limited.
Abstract: A receiver having, arranged in this order, an input section, an FM demodulator, to which a frequency-modulated input signal is applied, and an LF section, which FM demodulator includes a pulse shaper and a low-pass filter, the pulse shaper comprising a series arrangement of at least a load and a capacitance, the base-emitter junction of a transistor being arranged across the capacitance, and further including a switching device for charging and discharging the capacitance The pulse shaper generates a low-noise pulse in that charging of a capacitance is started upon an edge of the input signal The capacitance voltage is measured by a single transistor and when the transistor is turned on, the charging current of the capacitance is diverted via the transistor, so that the capacitance voltage is limited The capacitance is discharged upon a second edge, after which the cycle is repeated The output signal of the pulse shaper is a signal which varies with the current through the capacitance

61 citations

Patent
David R. Welland1
29 May 1998
TL;DR: In this article, a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) was proposed to synthesize high-frequency signals, such as wireless communication signals.
Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. The continuously variable capacitance may be formed by using a plurality of separate capacitance circuits. The individual capacitance circuits may include two capacitors coupled to a variable resistance element. The variable resistance element may be a transistor controlled by an analog control voltage. The total capacitance of the continuously variable capacitance may be substantially linear with respect to the phase of the VCO output while the individual capacitance circuits exhibit nonlinear behavior.

61 citations

Proceedings ArticleDOI
24 Jul 2006
TL;DR: This paper proposes a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE and is seen to be effective in a wide variety of C NFET structures as well as for a wide range of operating conditions in the digital circuit application domain.
Abstract: With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.

61 citations

Journal ArticleDOI
TL;DR: An easy-to-design interface circuit to measure very small-percentage capacitance variations in capacitive sensors, especially suitable for industrial measurements, and minimizes the error caused by coupling and stray capacitance of sensor probes.
Abstract: This paper presents an easy-to-design interface circuit to measure very small-percentage capacitance variations in capacitive sensors, especially suitable for industrial measurements. A computer-controlled 24-bit A/D converter is employed to obtain a higher resolution. This interface circuit can be used with various types of capacitive sensors. The most interesting thing is, that the measurement results through this interface circuit are independent of the initial capacitance of the sensor. In addition, the double differential operating principle used here minimizes the error caused by coupling and stray capacitance of sensor probes. The operating principle of the designed interface circuit, the major assumptions made, test data, and possible future developments are discussed.

61 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202364
2022156
2021179
2020344
2019380
2018382