Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

High-efficiency adaptive DC/AC converter

Abstract: A CCFL power converter circuit is provided using a high-efficiency zero-voltage-switching technique that eliminates switching losses associated with the power MOSFETs. An optimal sweeping-frequency technique is used in the CCFL ignition by accounting for the parasitic capacitance in the resonant tank circuit. Additionally, the circuit is self-learning and is adapted to determine the optimum operating frequency for the circuit with a given load. An over-voltage protection circuit can also be provided to ensure that the circuit components are protected in the case of open-lamp condition.

A 6- $\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Abstract: An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

Hardware design of electrical capacitance tomography systems

Abstract: Electrical capacitance tomography (ECT) was one of the techniques which were firstly developed for process tomography (PT) Two types of capacitance measuring circuits are the most suitable for the use in ECT systems - the charge/discharge circuit and the AC-based circuit - because of their immunity to stray capacitance Since the standing capacitances involved are relatively large and the capacitance changes to be measured are very small, the standing values need to be cancelled by DC offset compensation or AC feedback compensation Alternatively, the capacitances can be measured by high-accuracy self-balancing circuits without standing value compensation In this paper different designs of sensing electronics for ECT systems are presented and the advantages and disadvantages compared

A methodology and model for the pull-in parameters of electrostatic actuators

Abstract: This paper presents a generalized model for the pull-in phenomenon in electrostatic actuators with a single input, either charge or voltage. The pull-in phenomenon of a general electrostatic actuator with a single input is represented by an algebraic equation referred to as the pull-in equation. This equation directly yields the pull-in parameters, namely, the pull-in voltage or pull-in charge and the pull-in displacement. The model presented here permits the analysis of a wide range of cases, including nonlinear mechanical effects as well as various nonlinear, nonideal, and parasitic electrical effects. In some of the cases, an analytic solution is derived, which provides physical insight into how the pull-in parameters depend upon the design and properties of the actuator. The pull-in equation can also yield rapid numerical solutions, allowing interactive and optimal design. The model is then utilized to analyze analytically the case of a Duffing spring, previously analyzed numerically by Hung and Senturia, and captures the variations of the pull-in parameters in the continuum between a perfectly linear spring and a cubic spring. Several other case studies are described and analyzed using the pull-in equation, including parallel-plate and tilted-plate (torsion) actuators taking into account the fringing field capacitance, feedback and parasitic capacitance, trapped charges, an external force, and large displacements.

Calculation and measurement of electromechanical coupling coefficient of capacitive micromachined ultrasonic transducers

Abstract: The electromechanical coupling coefficient is an important figure of merit of ultrasonic transducers. The transducer bandwidth is determined by the electromechanical coupling efficiency. The coupling coefficient is, by definition, the ratio of delivered mechanical energy to the stored total energy in the transducer. In this paper, we present the calculation and measurement of coupling coefficient for capacitive micromachined ultrasonic transducers (CMUTs). The finite element method (FEM) is used for our calculations, and the FEM results are compared with the analytical results obtained with parallel plate approximation. The effect of series and parallel capacitances in the CMUT also is investigated. The FEM calculations of the CMUT indicate that the electromechanical coupling coefficient is independent of any series capacitance that may exist in the structure. The series capacitance, however, alters the collapse voltage of the membrane. The parallel parasitic capacitance that may exist in a CMUT or is external to the transducer reduces the coupling coefficient at a given bias voltage. At the collapse, regardless of the parasitics, the coupling coefficient reaches unity. Our experimental measurements confirm a coupling coefficient of 0.85 before collapse, and measurements are in agreement with theory.