Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

An Improved Stray Capacitance Model for Inductors

Abstract: This paper proposes an improved analytical stray capacitance model for inductors. It considers the capacitances between the winding and the central limb, side limb, and yoke of the core. The latter two account for a significant proportion of the total capacitance with the increase of the core window utilization factor. The potential of the floating core/shield is derived analytically, which enables the model to apply not only for the grounded core/shield, but also for the floating core/shield cases. On the basis of the improved model, an analytical optimization method for the stray capacitance in inductors is proposed. Moreover, a global Pareto optimization is carried out to identify the tradeoffs between the stray capacitance and ac resistance in the winding design. Finally, the analysis and design are verified by finite element method simulations and experimental results on a 100-kHz dual active bridge converter.

An exhaustive method for characterizing the interconnect capacitance considering the floating dummy-fills by employing an efficient field solving algorithm

Abstract: This paper presents an exhaustive method to characterize the interconnect capacitances while taking the floating dummy-fills into account. Results of the case study with typical floating dummy-fills show that the inter-layer capacitances are also an important factor in the electrical consideration for the dummy-fills. An efficient field solving algorithm is implemented into the 3D finite-difference solver and its computational efficiency is compared with the industry-standard RAPHAEL. Furthermore, the overall flow for extracting the parasitic capacitance considering the dummy-fills at the full-chip level is discussed and the underlying assumption is examined.

Inductor winding capacitance cancellation using mutual capacitance concept for noise reduction application

Abstract: In this paper, the properties of mutual capacitance between two capacitors are first discussed. It is found that the effects of mutual capacitance can be represented by two positive or negative capacitors across the two capacitors. These two equivalent capacitors can be used to cancel the parasitic capacitance of inductors. Because the mutual capacitance can be emulated using two small capacitors, the proposed method can easily be implemented in practical components. The prototypes are then built and the cancellation is verified using a network analyzer. Further EMI measurements in a practical power circuit prove that there is a significant improvement in the inductor's filtering performance.

Electronic circuit analysis and design

Abstract: Fundamentals of Electronic Circuit Analysis and DesignMicrowave Active Circuit Analysis and DesignElectronic Circuits (Sie) 3EIntroduction to Electrical Circuit AnalysisFoundations of Analog and Digital Electronic CircuitsFast Analytical Techniques for Electrical and Electronic CircuitsAnalog Circuit DesignElectronic CircuitsIntroduction to Linear Circuit Analysis and ModellingMicroelectronicsIntroduction to Circuit Analysis and DesignPower ElectronicsMicroelectronics Circuit Analysis and DesignElectronic Circuit Analysis and DesignComputer Methods for Circuit Analysis and DesignAnalysis and Design of Electronic Circuits Using PCsFundamentals of Electronics: Book 1Microelectronic Circuits: Analysis and DesignElectronic Circuit Analysis:Tolerance Design of Electronic CircuitsElectronics and Circuit Analysis Using MATLABIntuitive Analog Circuit DesignElectronic Circuit Analysis and DesignComputer Methods for Circuit Analysis and DesignElectronic Circuit Analysis and DesignCircuit AnalysisIntroduction to Electronic Circuit DesignAdvanced Electronic Circuit DesignElectronic Circuit Analysis and DesignMosfet Modeling for Circuit Analysis and DesignElectronic CircuitsCircuit Analysis For DummiesMicroelectronic CircuitsElectronic Circuit Analysis and DesignElectronic Circuit AnalysisElectronic Circuit Analysis and DesignElectronic Circuit DesignElectrical Circuit Analysis and DesignCircuitsElectronic Circuit Analysis and Design

Self-calibration method for capacitors in a monolithic integrated circuit

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted. In another aspect of the invention, capacitance-adjustment steps are sequentially interleaved with analog-to-digital conversions in an analog-to-digital converter.