Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Printed Spiral Winding Inductor With Wide Frequency Bandwidth

Abstract: Winding parasitic capacitance is a major factor limiting the bandwidth of an inductor. In this paper, 1) the traditional, 2) the alternating, and 3) the partial alternating winding methods are evaluated for the multilayer printed spiral winding inductors for megahertz operations. The self-capacitances of various winding structures are estimated by the summation of parasitic capacitance among the turns of a winding. The electric field energy distributions in the inductors are derived from the voltage profiles to illustrate the relative magnitudes of winding parasitic capacitances. The results show that parasitic capacitance reduction can be achieved by reducing stored electric field energy. The partial alternating winding method is found to have the widest frequency bandwidth with reduced number of through-hole vias for multilayer printed spiral winding design. The theoretical analysis has been confirmed with practical measurements. The results provide useful information for the optimal design of coreless or core-based high-frequency planar magnetics.

Accurate metallization capacitances for integrated circuits and packages

Abstract: The parallel-plate formula is widely used by the solid-state circuit designer to estimate capacitances in integrated circuits. Since considerable errors may result from using this approximation, this correspondence gives correction curves for a wide range of parameters. It is shown that the finite conductor thickness may significantly contribute to the increase in capacitance.

Capacitive sensor circuit with good noise rejection

Abstract: This invention describes the deficiencies of current art for sensitive impedance sensors, particularly capacitive sensors, and describes several circuits that improve measurement of small value capacitances, especially in the presence of noise. It also shows various circuit architectures optimized for different capacitive sensing tasks. The circuits also describe a novel method to linearize a conventional charge-transfer capacitive sense circuit and a novel method to eliminate the effect of stray capacitance in charge-transfer capacitive sensors.

Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Abstract: Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

Switched capacitor DSB modulator/demodulator

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90° phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal. This circuit is converted to a balanced modulator by omitting C5 and C6. In an alternate embodiment of a single sideband modulator that requires only a pair of switched capacitors C11 and C12, a 4-phase switch means alternately charges C11 and C12 with associated ones of the quadrature-phase input signal voltages while alternately connecting C12 and C11 as feedback capacitors across A1, the polarity of each capacitors feedback voltage being reversed each time that capacitor is connected across the amplifier. This circuit is operated as a balanced modulator by omitting one of the capacitors.