Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Simulation and structure optimization of triboelectric nanogenerators considering the effects of parasitic capacitance

Abstract: Parasitic capacitance is an unavoidable and usually unwanted capacitance that exists in electric circuits, and it is the most important second-order non-ideal effect that must be considered while designing a triboelectric nanogenerator (TENG) because its magnitude is comparable to the magnitude of the TENG capacitance. This paper investigates the structure and performance optimization of TENGs through modeling and simulation, taking the parasitic capacitance into account. Parasitic capacitance is generally found to cause severe performance degradation in TENGs, and its effects on the optimum matching resistance, maximum output power, and structural figures-of-merit (FOMs) of TENGs are thoroughly investigated and discussed. Optimum values of important structural parameters such as the gap and electrode length are determined for the different working modes of TENGs, systematically demonstrating how these optimum structural parameters change as functions of the parasitic capacitance. Additionally, it is demonstrated that the parasitic capacitance can improve the height tolerance of the metal freestanding-mode TENGs. This work provides a theoretical foundation for the structure and performance optimization of TENGs for practical applications and promotes the development of mechanical energy-harvesting techniques.

Fabrication of n‐ and p‐Type Organic Thin Film Transistors with Minimized Gate Overlaps by Self‐Aligned Nanoimprinting

Abstract: [∗] U. Palfi nger , C. Auner , H. Gold , A. Haase , J. Kraxner , G. Jakopic , J. R. Krenn , B. Stadlober Institute of Nanostructured Materials and Photonics Joanneum Research GmbH Franz-Pichlerstrasse 30, A-8160 Weiz (Austria) Fax: 0043-316-876-2710 Telephone: 0043-316-876-2721 E-mail: barbara.stadlober@joanneum.at T. Haber , M. Sezen , W. Grogger Institute for Electron Microscopy Graz University of Technology Steyrergasse 17, A-8010 Graz (Austria) G. Domann Fraunhofer-Institut für Silicatforschung ISC Neunerplatz 2, D-97082 Würzburg (Germany)

Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input

Abstract: In low power current mode signal processing circuits it is often necessary to use current mirrors to replicate and amplify/attenuate current signals and clamp the voltage of nodes with high parasitic capacitances so that the smallest currents do not introduce unacceptable delays. The use of tunable active-input current mirrors would meet both requirements. In conventional active-input current mirrors, stability compensation is required. Furthermore, once stabilized, the input current cannot be made arbitrarily small. In this paper we introduce two new active-input current mirrors that clamp their input node to a given voltage. One of them does not require compensation, while the other may under some circumstances. However, for both, the input current may take any value. The mirrors can operate with their transistors biased in strong inversion, weak inversion, or even as CMOS compatible lateral bipolar devices. If it is biased in weak inversion or as lateral bipolars, the current mirror gain can be tuned over a very wide range. According to the experimental measurements provided in this paper, the input current may spawn beyond nine decades and the current mirror gain can be tuned over 11 decades. As an application example, a sinusoidal g/sub m/-C-based VCO has been fabricated, whose oscillation frequency could be tuned for over seven decades, between 73 mHz and 1 MHz.

Sub-micrometer-sized, cross-type Nb–AlOx–Nb tunnel junctions with low parasitic capacitance

Abstract: We report on a technology for the fabrication of sub-micrometer sized cross-type Josephson tunnel junctions in niobium technology. We present the fabrication scheme and properties of cross-type junctions with linear dimensions from 10 down to 0.6??m. Sidewall passivation of the junctions is achieved by anodization as well as by planarizing the junctions with SiO in a self-aligned deposition step. The measured ratio of the sub-gap resistance to the normal resistance is about 35. Because of their low sub-gap current and low parasitic capacitance such junctions are well suited for applications like high resolution SQUIDs.

A 114GHz VCO in 0.13 /spl mu/m CMOS technology

Abstract: A differential transimpedance amplifier combined with a positive feedback compensation circuit tolerates 1.5pF parasitic capacitance from ESD protection in 0.35 /spl mu/m SiGe BiCMOS. A 2.5Gb/s receiver demonstrates 15k/spl Omega/ transimpedance gain and DR from -3 to -23.5dBm while consuming 21mW from a 3V supply.