Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Common-Ground-Type Five-Level Transformerless Inverter Topology With Full DC-Bus Utilization

Abstract: Transformerless inverters (TIs) are widespread in photovoltaic (PV) applications due to their low cost and high efficiency. However, TIs suffer due to leakage current as a consequence of PV parasitic capacitance, and high-frequency common-mode voltage, which has resulted in the emergence of several topological and control scheme modifications. In this article, a switched-capacitor (SC) based inverter capable of synthesizing a five-level voltage is proposed. In the devised structure, the negative pole of the dc bus is directly connected to the grid neutral, thereby resulting in zero leakage current. In addition, industrial standard half-bridge modules can be employed directly for implementing the proposed inverter without modifications, making it more practically feasible. The proposed topology has the capability of self-voltage balancing of SC, reactive power processing, and full dc-bus utilization as opposed to half-bridge topologies. The principle of operation and a simple logic-gate-based pulse generation scheme is presented in detail. Simulation and experimental results confirming the practical viability of the proposed topology are presented. Finally, the superior features and the merits of the proposed topology are shown through a detailed comparison against state-of-the-art topologies.

Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs

Abstract: In this paper, an analytical model for parasitic gate capacitances in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is developed for the first time. A practical 3-D architecture of SNWTs with surrounding-gate cylindrical channel and source/drain extension regions is taken into account in the parasitic gate capacitance modeling. The parasitic gate capacitances of the SNWT are divided into four parts: 1) outer fringe capacitance Cof; 2) inner fringe capacitance Cif; 3) overlap capacitance Cov; and 4) sidewall capacitance Cside. The 3-D capacitance system is calculated by useful methods such as the equivalent transformation and inversion of Schwarz-Christoffel mapping. The obtained model agrees well with the results of 3-D electrostatic numerical simulations. The results show that the proportion of parasitic gate capacitances in the total capacitance is increased in this gate-all-around architecture due to the ultrasmall dimension of the SNWT channel; thus, the proportion of the intrinsic capacitance is reduced. Among the capacitances, Cof is found to be the largest contributor to the total parasitic gate capacitance in FO1 delay calculation, and Cside manifests itself as a nonnegligible parasitic capacitance. The developed capacitance model can be easily incorporated into a compact core model of SNWTs for further device/circuit design optimizations with various device parameters.

A Comprehensive Analysis and Modeling of the Self-Powered Synchronous Switching Harvesting Circuit With Electronic Breakers

Abstract: Self-powered realization for synchronous switching circuits is a hot spot for piezoelectric vibration energy harvesting. As a well-known approach, the electronic breaker is widely used for its simplicity and reliability. It plays an important role on the performance of the piezoelectric generator by affecting the available open-circuit voltage and the switching phase lag. In this paper, a comprehensive model is developed for improved performance analysis with missed factors included in comparison with previous investigations. The combined influence of the envelope resistor and the capacitor on both the phase lag and the open-circuit voltage is newly considered while the additional phase lag effect induced by charging the switch parasitic capacitance with the envelope capacitance is supplemented. Experiments and simulations validate the proposed model with better accuracy and the results show that these supplemented factors are important to the generator performance, especially for the micropower energy harvesting with small piezoelectric capacitance or displacement magnitude. Moreover, more detailed design guidelines are deduced from the proposed model.

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability

Abstract: SOI CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications compared to bulk CMOS. It is also emerging as a good candidate for high-performance SoC, with integratable RF circuits that operate beyond 30-GHz already demonstrated at the 130-nm technology node. The digital aspects of the base 90-nm SOI technology were previously reported. This paper presents the RF performance of this technology, and shows that the capabilities of CMOS technology are expanding into the millimeter-wave regime.