Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Test point monitor using embedded passive resistance

Abstract: Exemplary techniques for providing a test point in a printed circuit board (PCB) or other circuit device that minimizes or eliminates intrusive effects in the transmitted as well as the monitored data signal are disclosed. A deposited resistor is used to provide a connection between a signal electrode and a transmission line of the PCB. Where the transmission line is embedded, the PCB may also include a tap to connect the signal layer of the PCB (having the embedded transmission line) with the signal electrode at the surface layer of the PCB. The deposited resistor is intended to act as a voltage-divider resistor and to buffer any perturbations of the system resulting from the tap and the introduction of a probe. Additionally, the deposited resistor may be positioned relative to the transmission line as to provide a equalization capacitance to compensate for parasitic capacitance.

Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks

Abstract: The present invention relates to a device for protecting high frequency RF integrated circuits from ESD damage. The device comprises at least one varactor-LC circuit tank stacked to avoid the power gain loss by the parasitic capacitance of ESD circuit. The varactor-LC tank could be designed to resonate at the RF operating frequency to avoid the power gain loss from the parasitic capacitance of ESD circuit. Multiple LC-tanks could be stacked for further reduction in the power gain loss. A reverse-biased diode is used as the varactor for both purposes of impedance matching and effective ESD current discharging. Because the inductor is made of metal, both the inductor and the varactor can discharge ESD current when ESD condition happens. It has a high enough ESD level to prevent ESD discharge.

A 5.4-GHz high-Q tunable active-inductor bandpass filter in standard digital CMOS technology

Abstract: A transistor-only CMOS active-inductor with an all-NMOS signal path is presented. By tuning the varactor-augmented parasitic capacitance at the only internal node the circuit losses from submicron MOSFETs can be partially or fully compensated to permit realizing unlimited values of Q, with little frequency and no power-consumption penalties. Transistor-only second-order bandpass filters using the active inductor were built in the TSMC 0.18-μm CMOS process, and high filter Q was obtained by tuning the varactor. The highest center frequency measured was f 0 = 5.7 GHz for 0.2-μm gate lengths and the maximum repeatably measured Q was 665. Lower Qs can be obtained by reducing the capacitive compensation or by adjusting the circuit biasing. f 0 and Q are tunable via separate varactors. IIP 3 and input 1-dB compression point were simulated as 0.523 VPP and 0.128 VPP (?1.65 and ?13.9 dBm from a 50-? source) at 5.7 GHz with Q = 100 and midband gain equal 4.7 dB. For the same conditions, the output noise and noise figure (R S = 50 k?) were simulated to be 0.8 μV/Hz1/2 and 25.6 dB, respectively. The filter core occupies an area of 26.6 μm × 30 μm and dissipates 4.4 mW at 5.4 GHz from a 1.8-V power supply. As the circuits use only MOSFETs they are fully compatible with standard digital CMOS processes. f 0 statistics were obtained by measuring 40 chips at identical biasing condition.

On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area

Abstract: This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the serial-parallel, linear (LIN), Fibonacci, and 2N multipliers are compared. Results show that the LIN cell is the best for integration because of the smallest total capacitor area and the highest current efficiency under the assumption that the parasitic capacitance is not smaller than 10% of the multiplier capacitance, and the Fibonacci cell is the best for discrete application because of the minimum number of capacitor components with moderate current efficiency under the assumption that the parasitic capacitance is not larger than 1% of the multiplier capacitance.

Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors

Abstract: As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology