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Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.


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Patent
06 Sep 1991
TL;DR: In this article, a method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states.
Abstract: A method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states. Using parasitic capacitance and transistor conductance values extracted from the circuit layout, this method and evaluates driving-point resistances and delays in an RC-network representation of the complete circuit.

50 citations

Journal ArticleDOI
TL;DR: In this paper, an array of devices that map the strain field on a flexible polyvinylidene difluoride (PVDF) film surface is demonstrated, which can be detected even in the presence of parasitic capacitance.
Abstract: Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation, which have complicated the development of array-based polyvinylidene difluoride (PVDF) sensors. We have used organic field-effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer, i.e., PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal, which can be detected even in the presence of parasitic capacitance. The device couples the voltage generated by the PVDF film under strain into the gate of organic thin-film transistors using an arrangement that allows the full piezoelectric voltage to couple to the channel while also increasing charge-retention time. A bipolar detector is created using ultraviolet-ozone treatment to shift the threshold voltage and increase the current of the transistor under both compressive and tensile strain. An array of devices that maps the strain field on a PVDF film surface is demonstrated.

50 citations

Journal ArticleDOI
TL;DR: In this paper, a self-aligned top-gate oxide-semiconductor thin-film transistor (TFT) formed by using the aluminum reaction method has been developed, which has advantages such as small-sized TFTs, lower mask count, and small parasitic capacitance.
Abstract: — A novel highly reliable self-aligned top-gate oxide-semiconductor thin-film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small-sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4-μm channel length exhibited a field-effect mobility of 21.6 cm2/V-sec, a threshold voltage of −1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9-in.-diagonal qHD AMOLED display was demonstrated with self-aligned top-gate oxide-semiconductor TFTs for a low-cost and ultra-high-definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.

50 citations

Proceedings ArticleDOI
Wenfeng Cui1, Bo Yang1, Yi Zhao1, Wuhua Li1, Xiangning He1 
01 Nov 2011
TL;DR: In this article, a transformerless single-phase inverter with two unipolar SPWM control strategies is proposed, which can guarantee no ground leakage current and high reliability by applying either of the SPWM strategies.
Abstract: Nowadays, the transformerless inverters have become a widespread trend in the single-phase grid-connected photovoltaic (PV) systems because of the low cost and high efficiency concerns Unfortunately, due to the non-galvanic isolation configuration, the ground leakage current would appear through the PV parasitic capacitance into the ground, which induces the physical danger and serious EMI problems A novel transformerless single-phase inverter with two unipolar SPWM control strategies is proposed in this paper The inverter can guarantee no ground leakage current and high reliability by applying either of the SPWM strategies Meanwhile, the low total harmonic distortion (THD) of the grid-connected current is achieved thanks to the alleviation of the dead time effect Besides, the required input DC voltage is the same low as that of the full-bridge inverter Furthermore, the output filter inductance is reduced greatly due to the three-level output voltage, which leads to the high power density and high efficiency At last, a 1kW prototype has been built and tested to verify the theoretical analysis of the paper

50 citations

Patent
14 May 1990
TL;DR: In this paper, a relaxation oscillator is disclosed which includes first and second currents for charging and discharging a capacitor (50) wherein the slew rate of the dynamic voltages developed at the terminals of the capacitor ( 50) remain substantially constant for each frequency of operation which desensitizes the oscillator to the effects of the inherent stray capacitance, and improves the accuracy of output frequency.
Abstract: A relaxation oscillator is disclosed which includes first and second currents for charging and discharging a capacitor (50) wherein the slew rate of the dynamic voltages developed at the terminals of the capacitor (50) remain substantially constant for each frequency of operation which desensitizes the oscillator to the effects of the inherent stray capacitance, and improves the accuracy of the output frequency. A circuit (74,76,78,80) monitors the dynamic voltage across the capacitor (50) and inverts a control signal at opposite polarities of a particular threshold. A bistable circuit (86,88,90,92,94) provides first and second complementary output signals in response to the control signal from the circuit (74,76,78,80). The first and second complementary output signals drive a pair of switching transistors (52,54) which alternate the direction of current flowing through the capacitor (50) so as to provide smooth voltage transitions at the terminals of the capacitor (50).

49 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202364
2022156
2021179
2020344
2019380
2018382