Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Electrically tuned integrated amplifier for wireless communications

Abstract: An electrically tunable radio frequency (RF) amplifier includes a resonant circuit having a voltage variable capacitance as one of its elements. In one approach, a drain diffusion capacitance of one of the transistors within the amplifier is used as the voltage variable capacitance. A voltage adjustment unit is provided to adjust a bias voltage on the voltage variable capacitance to change the capacitance value thereof and thus modify the operating frequency range of the amplifier. In one embodiment, the voltage adjustment unit also provides a power supply noise blocking function.

Current equalizer assembly for LCD backlight panel

Abstract: A current equalizer assembly for LCD backlight panel comprises at least a differential current choke and at least a capacitor. The capacitor is arranged striding on a terminal (B) at a primary coil and on a terminal (D) at a secondary coil of the differential current choke so as to equalize the current flowing through every cold cathode fluorescent lamp (CCFL) connected to the differential current choke and the lightness thereof accordingly. Moreover, the capacitance of the stridden capacitor is replaceable by the intrinsic stray capacitance when the inductance of the differential current choke is properly selected.

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability

Abstract: Silicon-based CMOS is the dominant technology choice for high-performance digital circuits. While silicon technology continues to scale, researchers are investigating other novel materials, structures, and devices to introduce into future technology generations, if necessary, to extend Moore's law. Carbon nanotubes (CNTs) have been explored as a possibility due to their excellent carrier mobility. The authors studied and compared different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective. Parasitics play a major role in the performance of CNT-based circuits. The data in this paper show that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors. Transient analysis of high-performing single-tube SB CNFET transistors and circuits revealed that 1-1.5 nm is the optimum CNT diameter resulting in best power-performance tradeoff for high-speed digital applications. The authors determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. CNTs have an intrinsic capability to improve performance, but many serious technological and experimental challenges remain that require more research to harvest their potential

Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets

Abstract: A method, apparatus and computer program product performs a bounded parasitic extraction of typically all nets in an integrated circuit as part of a series of post-layout verification operations. According to one embodiment, a resistance-only extraction and/or a capacitance-only extraction is initially performed using computationally inexpensive electrical models of the nets. The resistance and capacitance extractions may be combined with models of the active devices to generate realistic worst case and best case delay models for each of the extracted nets. The delay models may be based on the resistance-only extraction and an upper bound on the parasitic capacitance of the net determined from the capacitance-only extraction, however, other models based solely on a resistance-only extraction may also be used, although they are typically less preferred. A user-specified timing error tolerance is then used to automatically determine the appropriate level of additional extraction detail to be applied to the specific nets in the integrated circuit. This gives the user direct error control over the extraction process so that the extracted netlist meets the user-specified timing error tolerance in an efficient manner.

Method of fabricating an integrated thick film electrostatic writing head incorporating in-line-resistors

Abstract: An improved electrographic writing head employs interleaved arrays of writing nibs and small geometry, high impedance, thick film resistors and semiconductor driver circuits fabricated on a glass epoxy substrate. The writing head achieves significant savings in manufacturing costs by using low cost printed circuit and thick film technology. Power consumption may be reduced by more than half over prior art devices due to the high impedance of each thick film pull up resistor coupled with a associated writing neb. A ground plane is disposed internally of the substrate and between adjacent arrays of writing nibs. The ground plane prevents electrical interaction between the substrates and prevents the formation of parasitic nib-to-nib capacitance by shunting parasitic capacitance currents to ground. The ground plane thus reduces the possibility of flaring and substantially eliminates inadvertent writing by adjacent nibs.