Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Optically induced switching in a p-channel double heterostructure optoelectronic switch

Abstract: The switching time of a double heterostructure optoelectronic switch is investigated using an optical input. A switch‐on time of 5–10 ps is obtained using a discrete microwave package. The fall time of 10 ns is limited almost totally by the parasitic capacitance of the package. The switching operation shows the unique ability to turn on and off with the incident optical signal.

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

Abstract: In recent years, the multigate field-effect transistor (FET) has emerged as the most viable contender for technology scaling down to the sub-10-nm nodes. The nonplanar nature of multigate devices, along with rapidly shrinking front-end-of-line (FEOL) and back-end-of-line (BEOL) features, has compounded the problem of parasitics extraction in future technology nodes. In this paper, for the first time, we address the above problem through a holistic 3-D-technology CAD (3-D-TCAD) flow for the extraction of FEOL/(FEOL+BEOL) capacitances in generic multigate circuit layouts, using a transport analysis-based approach. We investigate device-level parasitic capacitances in 3-D-process-simulated bulk and silicon-on-insulator FinFETs, and uncover capacitance scaling trends for candidate single/multifin multigate FETs along the 22-nm/14-nm/10-nm technology nodes. Leveraging automated structure synthesis algorithms, we synthesize 3-D multigate 6T SRAM structures using the process-simulated devices, and examine the effects of fin pitch, gate pitch, and fin count on circuit-level parasitics. Thereafter, we show that traditional segregated FEOL/BEOL modeling approaches fail to provide accurate estimates, by back-annotating 3-D-TCAD-extracted capacitances into mixed-mode write simulations of a 6T FinFET SRAM bitcell. Finally, using FinFET NAND2 logic gate delay simulations, we establish the fact that capturing parasitics accurately is as important as modeling device transport accurately, and that performance/dynamic behavior in multigate circuits is highly sensitive to both factors.

Radio capsule oscillator circuit

Abstract: This invention relates to a Colpitts oscillator circuit for a radio capsule of the type adapted to be swallowed by a patient for investigating a condition of the gastrointestinal tract. The circuit includes a transistor as the active element and a parallel resonant LC circuit including the series combination of a variable capacitance diode and first and second capacitors, the capacitance of the second capacitor being the larger of the two in order to provide the minimum amount of positive feedback required to cause stable oscillation. The capacitance of the first capacitor, which is connected between the diode and the transistor emitter, approximates that of the diode at the lowest voltage applied to the diode by a sensor device.

Achieving Stable Through-Silicon Via (TSV) Capacitance with Oxide Fixed Charge

Abstract: Through-silicon via (TSV) is an important enabler for future 3-D integration of integrated circuits. TSV typically contains a high-aspect-ratio metal via embedded in silicon and electrically isolated from the silicon by a layer of dielectric liner hence forming a metal-oxide-semiconductor structure. The parasitic capacitance introduced by TSV must be kept as low as possible for low latency signal transmission. It is also equally important to ensure that the capacitance within the operating voltage is stable. It is shown that careful process tuning can induce the appropriate oxide fixed charge (|Qf| ~ 8.4 × 1011 cm-2) in order to shift the CV curve such that the TSV capacitance is kept stable at the value of accumulation capacitance (Cox) within the operating voltage range of interest (~0-5 V).

Capacitive Sensor for Three-Axis Force Measurements and Its Readout Electronics

Abstract: A capacitive sensor that can detect both vertically and horizontally applied contact forces is proposed. The sensor is built on a flexible material (rubber), in which conductive materials are deposited, forming four separate variable capacitors. The overall result is a thin sensor that consists of four variable capacitors with increased mechanical flexibility and robustness and is characterized by a simple structure and manufacture. The interface electronics, which allows reducing the parasitic capacitance effects of the wires, is also described. The experimental tests performed in the aforementioned setup demonstrate that the three-axis capacitive force sensor and its readout circuit are valid concepts to be applied to several fields, ranging from health to robotics, among others.