Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Self-Aligned-Gate ZnO TFT Circuits

Abstract: We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin-film transistors (TFTs) with a gate-self-aligned process to fabricate high-speed circuits. The speed of our previous PEALD circuits (22 ns/stage) was largely limited by the parasitic capacitance between the gate and drain, and a selfaligned-gate process provides higher speed devices and circuits. In this letter, a backside exposure process was used to fabricate gate-self-aligned TFTs with a mobility of 20 cm2/V · s. The seven-stage self-aligned-gate PEALD ZnO TFT ring oscillators had a propagation delay of 9.8 ns/stage at a supply voltage of 18 V. These ring oscillators are similar in performance to the best reported saturated-load oxide-semiconductor circuits but with much longer channel length (> 5× longer).

Light-emitting display, driving method thereof, and light-emitting display panel

Abstract: A pixel circuit of an organic EL display includes a driving transistor for transmitting a driving current to an organic EL element. A first capacitor is connected between a gate and a source of the driving transistor, and a second capacitor is connected between the gate thereof and a boosting scan line. A voltage corresponding to a data current from a data line is stored in the first capacitor in response to a select signal from a selecting scan line. The voltage level of the boosting scan line is changed so that the voltage of the first capacitor is changed by coupling of the first and second capacitors. The driving current corresponding to the changed voltage flows to the organic EL element to emit light. As a result, the current flowing to the organic EL element can be controlled using a large data current, and the influence of the parasitic capacitance components of the transistors or data lines can be minimized.

A 200- $\mu$ V/e $^{-}$ CMOS Image Sensor With 100-ke $^{-}$ Full Well Capacity

Abstract: A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e- rms noise floor with 200-muV/e- conversion gain and 100-ke- full-well capacity.

Program controlled capacitive keyboard variable threshold sensing system

Abstract: A sensing apparatus for detecting impedance changes in a variable impedance matrix keyboard. A microcomputer is utilized to control the basic key intersection scanning and for accurately calibrating and adjusting the sensing threshold of the sense amplifier prior to testing each key intersection so that the effects of stray impedance and varying voltage levels may be compensated for. The micro computer supplies sense amplifier sensitivity threshold selection address codes to set the sensing level for the amplifier. Trial drive pulses are applied to a reference capacitor and are gated to the sense amplifier while the sensing level thereof is varied until no output is obtained. This effectively adjusts the sensing circuits for variable voltage power fluctuations occurring over a short time and compensates for variable capacitive effects not associated with actual key switch movements. The micro computer also has a memory containing known stray capacitance values associated with a given keyboard design and these values are also used to compensate by modifying the sensing threshold above or below the calibrated sensing level achieved. Thisis done after driving and measuring the capacitance response until a zero output is obtained so that the sensing level may be individually set for each given key in the matrix at that precise level which can provide the highest non-saturating sensitivity level for the amount of stray capacitance known to be associated with the key and for the existing power and capacitance conditions as originally determined by checking the reference capacitor.

Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETs

Abstract: This paper examines self-heating trends in ultra-scaled fully depleted SOI and GOI devices. We introduce a self-consistent model for calculating device temperature, saturation current and intrinsic gate delay. We show that the raised device source/drain can be designed to simultaneously lower device temperature and parasitic capacitance, such that the intrinsic gate delay (CV/I) is optimal. We find that a raised source/drain height approximately 3 times the channel thickness would be desirable both from an electrical and thermal point of view. Optimized GOI devices could provide at least 30 percent performance advantage over similar SOI devices, despite the lower thermal conductivity of the germanium layer.