Topic
Parasitic element
About: Parasitic element is a research topic. Over the lifetime, 3413 publications have been published within this topic receiving 34236 citations.
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TL;DR: The metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology as mentioned in this paper offers several benefits that enable scaling to sub-30-nm gate lengths.
Abstract: In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.
451 citations
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TL;DR: This paper reviews the experimental evidence behind a new failure mechanism recently identified in GaN high-electron mobility transistors subject to electrical stress and suggests several paths to enhance the electrical reliability of GaN HEMTs.
Abstract: This paper reviews the experimental evidence behind a new failure mechanism recently identified in GaN high-electron mobility transistors subject to electrical stress. Under high voltage, it has been found that electrically active defects are generated in the AlGaN barrier or at its surface in the vicinity of the gate edge. These defects reduce the drain current, increase the parasitic resistance and provide a path for excess gate current. There is mounting evidence for the role of the inverse piezoelectric effect in introducing mechanical stress in the AlGaN barrier layer and eventually producing these defects. The key signature of this mechanism is a sudden and non-reversible increase in the gate leakage current of several orders of magnitude. This degradation mechanism is voltage driven and characterized by a critical voltage below which degradation does not occur. This hypothesis suggests several paths to enhance the electrical reliability of GaN HEMTs which are borne out by experiments.
390 citations
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TL;DR: In this article, the authors analyzed the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, s/D geometry-based analytical model, which was validated using three-dimensional device simulations and experimental results.
Abstract: The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.
342 citations
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TL;DR: In this article, the effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon thin film transistors (TFTs), and the results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance.
Abstract: The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage‐modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.
322 citations
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IBM1
TL;DR: In this article, a fabrication method that attains the "ideal" double-gate MOSFET device structure is reported, where the top and bottom gates are inherently self-aligned to the source/drain.
Abstract: In this paper, we report a fabrication method that attains the "ideal" double-gate MOSFET device structure. The top and bottom gates are inherently self-aligned to the source/drain. The source/drain is a fanned-out source/drain structure, which provides a low parasitic resistance. Channel silicon thickness is determined by a planar film deposition process with good uniformity control in principle. N-channel double-gate MOSFET's with a 25 nm thick silicon channel were successfully demonstrated.
300 citations