Parasitic element

About: Parasitic element is a research topic. Over the lifetime, 3413 publications have been published within this topic receiving 34236 citations.

Overview and status of metal S/D Schottky-barrier MOSFET technology

Abstract: In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. These and other benefits accrue using a low-thermal-budget CMOS manufacturing process requiring two fewer masks than conventional bulk CMOS. The SB-CMOS manufacturing process enables integration of critical new materials such as high-k gate insulators and strained silicon substrates. SB MOSFET technology state of the art is also reviewed, and shown to be focused on barrier-height-lowering techniques that use interfacial layers between the metal S/Ds and the channel region. SB-PMOS devices tend to have superior performance compared to NMOS, but NMOS performance has recently improved by using ytterbium silicide or by using hybrid structures that incorporate interfacial layers to lower the SB height.

Analysis of the parasitic S/D resistance in multiple-gate FETs

Abstract: The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

Reducing Mutual Coupling of MIMO Antennas With Parasitic Elements for Mobile Terminals

Abstract: Mutual coupling is a critical problem in the design of MIMO antennas because it deteriorates the performance of MIMO systems, which not only affects the antenna efficiency but also influences the correlation. Therefore, in this paper, using parasitic elements to reduce mutual coupling is studied. By adding parasitic elements a double-coupling path is introduced and it can create a reverse coupling to reduce mutual coupling. As an example, a dual-slot-element antenna with parasitic monopoles for mobile terminals is described. The discussion on channel capacity shows that the antenna can be considered as a good candidate for MIMO systems. Furthermore, based on the study of current distributions, it is concluded that the technique is sensitive to relative positions between parasitic elements, and relative positions between active element and parasitic element. Finally, we also extend the technique to a tri-element antenna.

An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

Abstract: The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage‐modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.