Topic

# Pass transistor logic

About: Pass transistor logic is a research topic. Over the lifetime, 9258 publications have been published within this topic receiving 149704 citations. The topic is also known as: PTL.

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TL;DR: This work demonstrates logic circuits with field-effect transistors based on single carbon nanotubes that exhibit a range of digital logic operations, such as an inverter, a logic NOR, a static random-access memory cell, and an ac ring oscillator.

Abstract: We demonstrate logic circuits with field-effect transistors based on single carbon nanotubes. Our device layout features local gates that provide excellent capacitive coupling between the gate and nanotube, enabling strong electrostatic doping of the nanotube from p-doping to n-doping and the study of the nonconventional long-range screening of charge along the one-dimensional nanotubes. The transistors show favorable device characteristics such as high gain (>10), a large on-off ratio (>10(5)), and room-temperature operation. Importantly, the local-gate layout allows for integration of multiple devices on a single chip. Indeed, we demonstrate one-, two-, and three-transistor circuits that exhibit a range of digital logic operations, such as an inverter, a logic NOR, a static random-access memory cell, and an ac ring oscillator.

2,642 citations

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TL;DR: “Spintronics,” in which both the spin and charge of electrons are used for logic and memory operations, promises an alternate route to traditional semiconductor electronics.

Abstract: “Spintronics,” in which both the spin and charge of electrons are used for logic and memory operations, promises an alternate route to traditional semiconductor electronics. A complete logic architecture can be constructed, which uses planar magnetic wires that are less than a micrometer in width. Logical NOT, logical AND, signal fan-out, and signal cross-over elements each have a simple geometric design, and they can be integrated together into one circuit. An additional element for data input allows information to be written to domain-wall logic circuits.

1,955 citations

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TL;DR: Bipolar voltage-actuated switches, a family of nonlinear dynamical memory devices, can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq.

Abstract: The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

1,642 citations

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TL;DR: Logic gates were fabricated from an array of configurable switches, each consisting of a monolayer of redox-active rotaxanes sandwiched between metal electrodes, which provided a significant enhancement over that expected for wired-logic gates.

Abstract: Logic gates were fabricated from an array of configurable switches, each consisting of a monolayer of redox-active rotaxanes sandwiched between metal electrodes. The switches were read by monitoring current flow at reducing voltages. In the “closed” state, current flow was dominated by resonant tunneling through the electronic states of the molecules. The switches were irreversibly opened by applying an oxidizing voltage across the device. Several devices were configured together to produce AND and OR logic gates. The high and low current levels of those gates were separated by factors of 15 and 30, respectively, which is a significant enhancement over that expected for wired-logic gates.

1,553 citations

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23 Jun 2002

TL;DR: An end-to-end model is described and validated that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs and predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SERper chip of unprotected memory elements.

Abstract: This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

1,506 citations