Showing papers on "Pass transistor logic published in 1967"

Testing for faults in combinational cellular logic arrays

Abstract: Cellular logic arrays are beginning to take on an increasingly greater importance in digital technology, mainly because of their numerous advantages for the design, manufacture, and use in digital systems employing large-scale integrated semiconductor arrays. Particularly significant among these advantages is the feature of testability. One would naturally expect that the iterative structure and the short intercell connections of a cellular logic array would allow it to be tested from its edge terminals much more easily than a relatively disorganized interconnection of the same number of gates. In this paper we confirm this conjecture, and we describe procedures for deriving minimal (or near-minimal) schedules of test inputs, to be applied to a combinational cellular array in order to detect the presence of any single faulty cell. In addition, necessary and sufficient conditions are presented for some types of arrays of unilaterally connected, identical cells to be completely testable for single faults. For one-dimensional arrays, these conditions are based upon known results in sequential network theory. For two-dimensional arrays, a relationship to the "domino problem" (which is known to be insoluble) is described, but is shown to be largely avoidable and nonrestricting in the present case.

Large Scale Integration of MOS Complex Logic: A Layout Method

Abstract: Large scale integration of complex logic is generally assumed to be a compromise between two conflicting cost factors, i.e., reduced design time through layout standardization, and increased yield through high circuit density, A unique but rather simple layout method is described that combines layout standardization with high circuit density generally expected from customized layout. At the same time, the design of the personality (the desired interconnection pattern) is simplified, while using a single layer of metallization. The method has been applied to complex logic using MOS NOR circuits.

Logic and memory elements using two-valley semiconductors

Abstract: Experimental results are given for bulk n-GaAs diodes when used as a two-state memory element and as a logic gate. An additional contact near the cathode improves the triggering sensitivity and isolates the input from the output. Bulk devices will ultimately operate at higher speeds than junction devices.

High speed logic circuits and method of constructing the same

Abstract: A logic inverter having a transistor emitter follower output circuit and an input circuit including therein a multicollector transistor or two transistors whose bases and emitters are connected in parallel with each other. In the inverter, the two collectors of the multicollector transistor or of the two transistors in the input circuit are connected to the base and the emitter, which is the output terminal, of the emitter follower transistor, respectively. A plurality of such inverters are combined in such a manner that the bases and the output terminals of the emitter follower transistors are connected in multiple to provide a logic circuit.

Temperature correction of a logic circuit arrangement

Abstract: A temperature compensated logic circuit having two transistors with commonly connected emitters and a third transistor, the collector-emitter path of which connects the emitters of the two transistors through a resistance to one terminal of a two terminal source of supply. A voltage divider having two taps is connected between the terminals, one tap being connected to the base electrode of one of the two emitter-connected transistors. The temperature compensation is through a barrier layer connecting the base electrode of the third transistor to the other divider tap, while a resistance further connects the base electrode of the third transistor to the other supply terminal.

High speed, low power, dynamic shift register with synchronous logic gates

Abstract: A shift register having a plurality of bits each formed by a pair of serially interconnected synchronous inverter stages operated by nonconcurrent clock pulses. Each inverter has an MOS transistor driver, a capacitive load, and a bilateral MOS transistor output. The shift register is in integrated circuit form on the (110) crystallographic plane with the current flow in all transistors in a direction normal to the (110) crystallographic plane. The logic input is the gate of the MOS transistor driver. The clock pulses are sequentially applied to the two inverter stages so that the logic number is shifted through the bit in two steps. Each clock pulse is applied across the load and driver and also is applied to the gate of the output transistor of the respective stage. ''''Fill,'''' ''''Clear,'''' and ''''Recirculate'''' modes are provided by NAND and NOR logic gates formed in the first bit by connecting two or more MOS transistor drivers for the inverter stages in series or in parallel, respectively. The last stage of the last bit is a unique high speed DC buffer capable of driving a highly capacitive circuit external to the shift register at high speed. This invention relates generally to MOSFET integrated circuits, and more particularly relates to a high speed shift register utilizing capacitively loaded, synchronous logic circuits.

Batch fabricated integrated all-magnetic logic

Abstract: All-magnetic logic is known for its very high reliability, but this logic has serious drawbacks: wiring cost, high power dissipation, etc The use of very thin laminated magnetic sheets and an integrated fabrication process solves all these problems Very low cost, power, size, and weight and a high reliability can be obtained by this technique An experimental integrated 2-bit shift register has been fabricated

Pulse Noise Immunity in Saturated Logic Gates

Abstract: This paper develops techniques for assessing the inherent pulse noise immunity of saturated logic gates, with a view towards determining their ability to operate reliably in a pulse noise environment. A test method has been outlined for specifying and measuring this noise immunity. Although this method is applicable to all forms of saturated logic, the low level T /sup 2/ L gate has been singled out for experiment because of its high speed capability. Using both discrete component and microcircuit gates of this type, close correlation was obtained between experimental results and calculations based on internal parameters of the individual devices.

Rapid switching logic gates

Abstract: A logic gate is described in which a transistor may be switched both on and off at extremely high speeds. The gate includes at least two pairs of elements, with each pair consisting of a negative resistance device and a matching resistor. The first pair is connected in the collector circuit and the second pair is connected in the emitter circuit of the transistor.

Improved micropower logic circuits

Abstract: Micropower transistor logic circuits designed to operate from power supply voltages which vary with temperature