Showing papers on "Pass transistor logic published in 1975"

MOSFET buffer for TTL logic input and method of operation

Abstract: An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL logic signals of 0.8 volts and 1.8 volts, is trapped on a reference storage node and the logic input voltage is trapped on a data input storage node. The two trapped voltages are then capacitively boosted by the same voltage to a level well above the transistor threshold voltage so that the differences in the voltage levels can be amplified, and the logic signal latched up by conventional circuitry. The voltage levels need be only momentarily boosted above the threshold level. The circuit includes a system for protecting against input voltage undershoot which includes another capacitive input storage node with a first trapping transistor between the logic input to the circuit and the second storage node and a second trapping transistor between the second storage node and the data input storage node. This prevents any degradation of voltage level on the data storage node should the input logic level momentarily be pulled more than one threshold below the level, typically ground, to which the gates of the transistors are taken after the voltage is trapped on the data node.

Substrate fed logic

Abstract: A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically for high packing density and low power-delay product. The basic logic element is a multi-input, multi-output gate, formed in a single-base land by using several diffused collectors and several Schottky base contacts. The lateral p-n-p injector of conventional I/SUP 2/L has been replaced by a vertical arrangement. Factors affecting packing density and power-delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. A preliminary process to demonstrate the feasibility of the vertical injector is described and the measured transistor parameters and power-delay product are given. Experiments to determine suitable conditions for the formation of Schottky barrier diodes are presented, and satisfactory performance for the complete process is demonstrated.

Schottky transistor logic

Abstract: Circuit/device concepts, evolving from MTL/I2L, that improve power delay and speed limits of superintegrated logic, will be discussed. Results from exploratory devices show the feasibility of the approach.

Self-biased trinary input circuit for MOSFET integrated circuit

Abstract: A trinary input circit for an MOSFET integrated circuit includes a biasing stage formed by using a standard inverter, whose output is connected to its input so as to establish a particular bias voltage level when the input to the trinary input circuit is left floating. The output of the biasing stage is applied to the inputs of a second inverter stage having a higher beta ratio than the bias stage and to the input of a third inverter stage having a lower beta ratio. The bias stage when left open circuited will seek a quiescent voltage which is above the switching threshold of the second stage and below the switching threshold of the third stage. Thus, as a result of the relative beta ratios of the three stages when the input to the bias stage is left open, the bias stage will seek a particular voltage level such that the high beta ratio stage produces a logic 0 output and the low beta ratio stage produces a logic 1 output. When a voltage greater than a certain value which is defined as a logic 1 is applied to the input, thus overriding the biasing stage, both the second and third inverter stages produce logic 0 outputs and, when a voltage less than a certain value which is defined as a logic 0 is applied to the input, to override the biasing stage, both inverters produce a logic 1. Three logic input conditions are therefore defined by two signals for use within the integrated circuit chip.

An experimental multiplier circuit based on superconducting Josephson devices

Abstract: This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.

Logic level decoding circuit

Abstract: In a digital system wherein digital data having two operating logic voltage levels corresponding to two different logic states is transmitted from one unit and received at another separate unit, circuitry is provided for determining the mean voltage value of the received logic voltage levels and for comparing the mean voltage value to the received data to provide decoding of the correct logic state of the individual signal bits.

Array logic macros

Abstract: A macro design approach is discussed which combines the cost-effective attributes of array logic structures with those of random logic. These macros utilize the following features: (a) internal feedback registers for performing sequential logic, (b) masking and submasking to reduce the number of words in the array for certain functions, (c) control of the array's output level to vary the apparent size of the array, (d) decoding on input pairs and/or EXCLUSIVE ORing on output pairs for increasing the number of logic levels, and (e) random-access memory in the feedback and its use in interrupt handling. The macros are explained by specific design examples. This paper also discusses standard logic circuits in combination with an array structure to produce a component that can be used efficiently in specific data processing areas. The designer may elect to define an array logic macro which is a combination of some of the features given in this paper. The guideline for this selection is based upon the features necessary in an array structure to bec ompetitive with a random logic LSI chip.

Detecting device for detecting battery outlet voltage

Abstract: A detecting device for detecting battery output voltage comprises a voltage detector having at least a pair of MOS transistors connected in series such that at least one of said MOS transistors shifts to its conductive state when the battery output voltage falls below a predetermined value to provide one type logic level signal and remains non-conductive when the battery output voltage is above the predetermined value to provide the other type logic signal. A switching circuit comprised of a complementary MOS inverter receives the output logic signal derived from the voltage detector and switches states in response to the two logic signals to accordingly control the energization of a display element in dependence upon the battery output voltage.

High performance MOS integrated circuit using the ion implantation technique

Abstract: Extensive use has been made of the advantages ion implantation has to offer over standard processing for the fabrication of high performance n-channel MOS circuits. By combining an enhancement driver with a depletion load, the maximum switching speed of FET logic elements has been evaluated for self-aligned structures with various channel lengths and various degrees of substrate decoupling via device-to-substrate capacitances. An 11-stage ring-oscillator circuit is used for performance evaluation. Switching delays as small as 115 ps were obtained for such inverter stages built on 200 /spl Omega//spl times/cm substrate material and having 1-/spl mu/m channel length. Essential fabrication details and circuit behaviors are described.

A high-speed ESFI SOS programmable logic array with an MNOS version

Abstract: A programmable logic array (PLA) with J-K flip-flops as feedback loops and having a maximum operating speed of 12 MHz has been designed and realized in epitaxial-silicon-films-on-insulators (ESFI) silicon-on-sapphire (SOS) technology. The advantages of the ESFI SOS technology and the circuit of the PLA are described and experimental results are presented. In addition, a twin PLA using metal-nitride-oxide-semiconductor (MNOS) transistors in the AND and OR matrices and having the same number of inputs, outputs, and feedback loops as the mask-programmable PLA has been designed. This MNOS PLA has full on-chip decoding capability and can be programmed or reprogrammed individually. The circuit of the MNOS PLA is described and the speed of the device is calculated.

Logic circuit for bistable D-dynamic flip-flops

Abstract: A logic circuit for dynamic D-flip-flop includes five n-channel MOS transistors and five p-channel MOS transistors. When used as a shift register stage, it works correctly without any additional delay element or capacitor. With two more MOS-transistors, the logic circuit works correctly with any sequence of input signals.

Tri-state logic circuit

Abstract: The conduction paths of two output complementary transistors are connected in series between first and second points of potential with the junction of the two transistors being connected to an output terminal. A control circuit responsive to control and data signals is connected to the two output transistors. In response to one condition of the control signal, the two output transistors are turned off by having connected between the control electrode (gate) and one end of the conduction path (source) of each one of them the conduction path of a different control transistor operated in a common switching (source) mode. In response to another condition of the control signal, the same logic signal is applied to the control electrodes of the two output transistors for turning one of them on by means of at least one of the control transistors operating in the common switching mode, to produce an output indicative of the data signal.

Schottky diode - complementary transistor logic

Abstract: A logic circuit uses an input Schottky diode of a first threshold and a clamp Schottky diode of a second threshold in combination with a high speed NPN switching transistor to form a simple high speed logic element. The novel use of two Schottky diodes of different threshold voltages provides a logic gate with a lower logic swing amenable with higher speed operation. Further, the operation of the logic gate is independent of the temperature characteristics of the NPN switching transistor. A PNP current source provides the drive current and load current for the logic gate in a simple manner which uses minimum chip area.

A flip-flop and logic gate with Josephson junctions

Abstract: A complementary logic circuit with Josephson junctions has been investigated theoretically and experimentally. This paper will discuss a circuit with a measured risetime of 100 ps, a power dissipation of 16.4 μW, with the flip-flop operated with a 1500-MHz input signal.

Applications of low-level differential logic

Abstract: Application of low-level differential logic will be discussed, citing a bipolar 8 × 8 bit multiplier with a 15-ns multiply time. The device LSI circuit uses either 2's complement or sign-magnitude binary number notation. A digital parallel correlator operating at a 150-MHz data rate has also been developed.

Complementary Josephson-junction circuit: a fast flip-flop and logic gate

Abstract: A logic circuit with Josephson junctions has been developed that operates as logic gate or as a flip-flop. Despite the latching-type characteristic of the Josephson tunnel junction, the complementary logic circuit is nonlatching. The test circuit has a power dissipation of 16.4 μW and a signal risetime of approximately 60 ps has been measured.

Current hogging injection logic-a new logic with high functional density

Abstract: A new design concept for bipolar integrated circuits with high functional density will be presented. The basic current hogging injection logic (CHIL) gate consists of a lateral intermediate collector structure, where the last collector simultaneously forms the base region of an inversely operated vertical output transistor. Thus a CHIL gate can be looked at as a CHL gate with a functionally integrated output transistor, or as an integrated injection logic (I/SUP 2/L) inverter with controlled injection. Dc and pulse measurements are discussed and calculated results with a simple model suitable for computer-aided design (CAD) are presented. The static noise immunity of CHIL circuits is compared to CHL and I/SUP 2/L. CHIL circuits are well suitable for large-scale integration (LSI) and are technologically compatible to all circuits fabricated in a standard buried collector (SBC) process.

A monolithic 8 pJ/2 GHz logic family

Abstract: Discusses a monolithic logic family developed for high-speed communication systems usage. The logic family affords 8 pJ speed-power product, 2 GHz toggle frequency and 400 ps/gate propagation delay time in 50/spl Omega/ transmission systems. The primary factor for realizing the high-speed, low-power operation is new circuit configuration: modified nonthreshold logic (NTL). Transistors in this circuit are made to operate almost in the active region which increases switching speed. In addition, a novel master slave flip-flop configuration is designed to operate with propagation delay nearly equal to that of gate. The device was fabricated by using junction isolated transistors with an emitter stripe width of 2 /spl mu/ and cutoff frequency of 4 GHz. This paper describes the circuit design and performance of developed logic family.

Logic level conversion system

Abstract: A circuit arrangement which permits interfacing logic systems operating on different logic levels and thus requiring different supply voltages in which the supply voltage for the logic system having the smaller signal excursion is obtained by means of a pair of zener diodes connected in series across the potential and reference potential of the logic system having a larger signal excursion to develop a potential and reference potential for the system having smaller signal excursions lying between the respective potential and reference potential levels of the system having larger excursions.

A System of Magnetic Bubble Logic

Abstract: By using two magnetic-bubble positions per bit it is possible to develop simple logical circuits which display essentially unlimited fan-in and fan-out. Systems of these circuits can be organized such that they conserve bubbles. Pipelining methods can be employed to enhance the throughput.

MOS logic circuit

Abstract: A MOS logic circuit includes a source follower circuit arrangement consisting of a driver MOS element, in addition to a transfer MOS element, an inverter MOS element and a load MOS element. The transfer MOS element receives input signals at its source and produces output signals at its drain, the output signals being applied to the gate of the driver MOS element contained within the source follower circuit arrangement. The resulting output signals developed at the source of the driver MOS element are supplied to the inverter MOS element. This permits the slice or boundary level between the logical 1 and 0 to be higher than the given threshold level of the MOS elements.

Some novel exclusive-OR/NOR circuits

Abstract: Some novel exclusive-OR/NOR-gate circuits are described that employ very few circuit components. They are also easily made in integrated-circuit form.

Microprocessor boolean processor

Abstract: A special purpose microprocessor with a limited number of functions, which can be used to interface between a central processor and a portion of a telephone exchange--for example, in line scanning. Six bit addressing and decoding are employed with two logic elements performing the few available programs. The processor includes a random access memory for intermediate storage, one logic unit and has capacity for 64 memory locations. The logic unit includes two NAND gates.

Distributed josephson junction logic circuit

Abstract: A distributed Josephson junction logic circuit is disclosed which includes a plurality of serially disposed Josephson junctions in a superconductive wire-over-groundplane environment wherein the latter is terminated at both ends in its characteristic impedance and energized at one end with a constant voltage source. In addition, at least one portion of the wire-over-groundplane transmission line, which is disposed in series with the junctions, is utilized as an output control and has the same steady state current flowing in it as the plurality of Josephson junctions. Utilizing such an arrangement, logic can be performed by means of multiple controls on a single junction as in terminated line logic or by means of several junctions, each with one or more independent controls, in series. The design is such that the switching of any one or more junctions to the voltage state causes a decrease in current from a level which represents a logical "1" to a lesser current which is representative of a logical "0". The resulting logic circuits may be latching or non-latching in character. When both ends of the distributed Josephson junction logic circuit are terminated in the characteristic impedance of the associated transmission line, inputs and outputs can be located at arbitrary points along the transmission line. The terminating resistors, returned at both ends of the line to points of low impedance to ground compared to the impedance of the terminating resistor, absorb transients originating on the power line or at any point along the transmission line. When any one or more of the inputs to such a circuit is a logical "1", at least one of the associated gates switches to the voltage state, reducing the output current to the logical "0" level. In a latching mode of operation, the circuit latches in that state until the gate current is momentarily quenched by reducing the power supply voltage. Thus, each stage normally inverts. The logic operation performed is a positive NOR, which is sufficient to implement any logical function. If desired, two or three controls can be used with some or all of the gates to perform such functions as inhibit, AND-OR-INVERT and majority and threshold logic. Logic circuits utilizing Josephson junctions operating at the gap which provide constant voltages are shown. In addition, circuit arrangements incorporating series-parallel powering circuits and the interconnection of logic circuits between more than one circuit arrangement are shown.

Test device for simultaneously displaying the level of logic signals in a plurality of circuits

Abstract: A test clip suitable for connection to a plurality of terminals at which appear respective logic signals representing those occurring in logic circuits provides an indication of the logic level of such signals. The circuit for effecting such indication is entirely self-contained requiring no external power source or grounding connection and includes a plurality of respective input lines connectable to such terminals with a respective indicator shunted by a reverse poled diode connected to each input line and one common connection for all the diodes and indicators. Thus, for example, a logic 1 signal occurring on one of the input lines will effect a current flow through a respective indicator to change the state thereof with a return current flow path being provided from the common connection through at least one of the shunting diodes connected to another input line then at logic 0 relatively ground potential. The circuit may be easily extended to test simultaneously as many circuits as desired, and such test circuit is effective to operate on positive logic as shown as well as on negative logic, the latter being achieved simply by reversal of the shunting diodes.

Charge transfer logic gate

Abstract: CHARGE TRANSFER LOGIC GATE A charge transfer logic gate comprises a plurality n of one-bit shift registers which fan-in to the series combination of a logic cell and an output cell. Each shift register comprises the series combination of two subcells, each of area A. The subcells are separated from one another, and from the logic cell, by potential barriers of magnitude VB established illustratively by ion implantation. The areas of the logic and output cells are both n x A and the two are separated by a threshold potential barrier of magnitude VT. To detect the presence of m and n inputs applied to separate ones of the shift registers (2< m

Analysis of load structures for current-mode logic

Abstract: Integrated circuit technology allows load characteristics to be shaped to the requirements of a circuit. Because it is possible to claim advantages for a variety of loads, a computer-aided analysis is used to relate the transient characteristics of a current-mode logic circuit to its static load line. A variety of load lines have been studied and an integrated diode-clamped-type load structure appears to offer the best static and dynamic characteristics.

Nonsaturated integrated injection logic

Abstract: Conventional integrated-injection-logic structures suffer from strong saturation of the n–p–n transistors. This increases the storage time, and hence puts a limitation on the propagation delay of the structures. A current-control technique is given to reduce this effect without changing the basic i.i.l. structure.

Supply dependent logic reset

Abstract: A circuitry for use with a power source which supplies energy to electronic equipment that uses logic circuitry where there is a requirement that the logic circuitry be inhibited when the power source is first activated and remain inhibited until the logic supply voltage level stabilizes at its final output voltage. Once this final voltage output level is reached the inhibited condition of the logic circuitry is removed and logic operation is initiated.