Showing papers on "Pass transistor logic published in 1976"

An associative logic matrix

Abstract: While retaining the regular interconnection structure of read-only memory and programmable logic array devices, associative logic makes possible the efficient realization of multiple output, multilevel, combinational, and sequential networks. The extreme versatility of associative logic is provided by internal feedback and matrix segmentation, both characteristic features of the new device. Internal feedback permits networks to be realized in two or more logic levels without the need for external output-input connections. It also makes practical the formation of memory circuits within the matrix. Segmentation permits formation of collinear but functionally independent line segments, thereby improving the areal efficiency of monolithic devices. Consideration of associative logic proceeds from a review of logic implementation by means of memory devices and concludes with a description of an associative logic device developed using bipolar technology.

High speed integrated injection logic (I/sup 2/L)

Abstract: High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.

Integrated programmable logic arrangement

Abstract: An integrated programmable logic arrangement is provided into which a logic pattern can be electronically written, and out of which a logic pattern can be electronically read-out. The logic arrangement has an AND-matrix, an OR-matrix, switching transistors in the AND and OR matrices comprising MI 1 I 2 S (metal-insulation 1-insulation 2-semiconductor) storage type transistors, and decoder means connected to the AND and OR matrices.

Fabrication of semiconductor integrated circuit structure including injection logic configuration compatible with complementary bipolar transistors utilizing simultaneous formation of device regions

Abstract: A version of integrated injection logic is disclosed in which both the switching transistor and the current source transistor are of the vertical type and in which the logic gates are fabricated in the same semiconductor integrated chip with linear circuits which are based on the complementary bipolar integrated circuit technology. The injection logic gate is fabricated simultaneously with the linear integrated circuit using selected steps of the complementary bipolar technology. High voltage linear circuits and efficient logic circuits are achieved based on the use of a single moderate resistivity N-type epitaxial layer deposited on a high resistivity P-type substrate. In the logic circuit portion the epitaxial layer forms the collector zone of the current source transistor and the base zone of the switching transistor.

Electric circuit control system using logic device

Abstract: A circuit is disclosed which is suitable for controlling lighting in a building from a multiple number of points AC current to light bulbs is controlled by a triac which in turn is controlled by the output of an optical coupler which is controlled by the output of a logic device The output of said logic device is connected to control the input to the triac Switches connecting to the input of the logic device each can independently determine energization or deenergization of the light bulbs

Complementary MOS logic circuit

Abstract: A complementary MOS logic circuit is disclosed. The circuit utilizes two stages with a coupling network comprising a capacitor and a diode used to couple the first stage to the second stage. This results in a circuit with the logic signal coupled to the input being inverted at the output without introducing substantial loss in signal amplitude.

Logic circuit arrangements using insulated-gate field effect transistors

Abstract: A clock pulse-controlled logic circuit arrangement wherein the source-drain path of a first transistor having its gate electrode supplied with a clock pulse and the source-drain paths of at least two second transistors jointly constituting a logic gate by having the respective gate electrodes supplied with data input are connected in series between a first and a second operating voltage supply point. To the junction of the first transistor and logic gate or an output point is connected an operation stabilizing circuit for replenishing the output point with a voltage signal having the same polarity as the output voltage signal to prevent any change in the level of the output voltage signal while the first transistor is rendered nonconducting.

Analysis of actual fault mechanisms in CMOS logic gates

Abstract: An analysis of failure modes in CMOS logic gates is presented. An example 3-input NAND gate is analyzed in detail and the ramifications of its failure modes are discussed.

Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

Abstract: As an approach to an advanced LSI logic, a high-speed and low-power femto-joule logic circuit has been developed by using an enhancement-type Schottky barrier gate FET (ESBT) with31P implanted channel layer. A direct coupled transistor logic (DCTL) was designed using ESBT and resistor as a basic logic circuit. To evaluate the dynamic performance of the logic circuit, a 15-stage ring oscillator with an output buffer was integrated on a chip. A power-delay product was found in the femto-joule range. The logic swing is about 0.4 V and typical noise margin is 30 percent of the logic swing. A high-speed (40 ns) and low-power (10 mW) 4 bit ALU has been developed by using DCTL, NOR gates. Furthermore, improving ESBT channel layer carrier profile to the higher carrier concentration and abruptly changing shallower carrier profile by31P and11B double implantation resulted in advanced characteristics of ESBT and logic circuit using it as follows. ESBT transconductance was increased by a factor of two. Power-delay product reduced to 80 percent of that of logic circuit, using ESBT with31P single implanted channel layer, was satisfactorily confirmed, together with a circuit density as large as 300 gates/ mm2.

Base drive boost circuit for improved fall time in bipolar transistor logic circuits

Abstract: An improved fall time is achieved in bipolar transistor logic circuits which have three-state outputs. The circuits comprise a logic input terminal which is coupled to a push-pull output stage to drive a three-state output terminal. A three-state input receives three-state control signals for holding the output transistors in their non-conducting, high impedance state. Improved speed is achieved by adding a feedback circuit to remove stored base charge from the upper output driver transistor and to supply base current derived from the load to the lower output driver transistor during high to low transitions of the output voltage.

Energy per logic operation in integrated circuits: definition and determination

Abstract: A figure of merit for the comparison of different types of logic circuits on the basis of inverters is presented. This figure of merit-the minimum energy per logic operation-is equal to the product of the time period necessary for carrying out a logic operation times the power which is fed into the inverter during this time period. Methods for the determination of these terms by ring oscillator measurements and model calculations are considered. In contrast to the so-called `delay-power' product, these newly defined terms are independent of the kind of measurement, as for example the number of stages of the ring oscillator. Thus the minimum energy per logic operation is an intrinsic figure of merit which allows a qualitative comparison of different types of logic circuits on a physical basis.

LSI layout and method for fabrication of the same

Abstract: An LSI layout includes a logic function section and a series connection array of two MOSFETs, one end of which array is coupled to a power source voltage and the other end of which array is coupled to ground potential. A fixed logic output is produced at a junction point of the two MOSFETs by providing one MOSFET as an enhance-type MOSFET and providing the other MOSFET as a depletion type MOSFET. A logic circuit is provided which is connected with the junction point of the MOSFET array and with the logic section and is operable to couple the output of the logic section to an output side thereof. Two logic sections may be respectively associated with two logic circuits one of which is operable to couple the output of one logic section to an output thereof for its practical use and the other of which is operable not to couple the output of the other logic section to an output side thereof. The selection of the used section and the unused section is determined by the selection of either one of MOSFETs to depletion type. The LSI layout further may include a circuit section including MOSFETs. In that case, a single mask may be used in introducing a selected MOSFET of the MOSFET array and selected MOSFETs of the circuit section as depletion types. Such an LSI layout is suitable for the manufacture of many different kinds of LSI layouts with a minimized number of fabrication masks.

Majority decision logic circuit

Abstract: A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits. A majority decision logic circuit comprises the elementary input signal circuits, the logic circuits and switching circuits, whereby the majority of outputs of a selected odd number of input signal circuits is decided. The abovesaid circuits can be formed with MOS transistors only, and are easily fabricated as an integrated circuit.

Folded-collector integrated injection logic

Abstract: Folded-collector I/SUP 2/L offers an effective method of controlling the saturation of the n-p-n transistor simply by controlling the ratio of two areas: the area of the output collector(s) and the area of a `dummy' collector. This extra collector is folded back and connected to the input base. The structure improves the minimum delay of the basic I/SUP 2/L gate. Moreover, the structure has many circuit applications where a current scaling factor is required, e.g., threshold and ternary logic. Some of these circuits are given.

Tri-state logic circuit

Abstract: A line driver including a pair of complementary transistors having their conduction paths serially connected between an operating and a reference potential and their bases connected through a first switch to a signal input terminal. A second switch is connected between the common base connection and the common connection of the conduction paths. With the second switch open and the first closed, an output voltage, responsive to the input signal, corresponding to first or second binary values is obtained. When the second switch is closed and the first opened, the transistor pair is turned off, disconnecting the line driver from its load, thereby providing tri-state logic operation.

Flip-Flops for Multiple-Valued Logic

Abstract: A family of multiple-valued (MV) electronic memory elements, referred to herein as flip-flops, is presented along with a system of MV algebra upon which they are based. These MV flip-flops are compared to binary flip-flops. MV asynchronous set-clear flip-flops and synchronous set-clear, D-type, JK, and modulo N counter flip-flops are presented, their next-state equations are derived, and they are shown to have desirable properties for use in MV sequential circuits. Experimental results and schematic diagrams are presented for a level restoring three-valued logic gate, the clocked set-clear flip-flop, and an example synchronous sequential circuit.

On Magnetic Bubble Logic Circuits

Abstract: This paper is concerned with the realization of logic functions by using two-input magnetic bubble logic elements. A magnetic bubble logic element is the multiple-output logic element whose number of ``1'' 's of the output is equal to that of corresponding input, and fanout of each output terminal of the element is restricted to one. In order to realize some functions, it is necessary to use the generators which correspond to constant-supplying elements. First, the number of generators which are necessary and sufficient to realize an arbitrary functions is obtained for a given set of elements. In particular, it is shown that an arbitrary function can be realized by using I B elements and at most two generators. Since the I B element is a universal element in the above sense and is considered to be rather easily realized by magnetic bubble interactions, the I B logic circuits are mainly discussed. The I B minimum circuit defined here is a circuit which consists of minimum number of generators and minimum number of I B elements. In the last half of this paper, it is shown that the minimum circuits of most functions have the characteristic circuit structure called ``1-4 form.''

Threshold logic gates

Abstract: A threshold logic gate comprises a digital summation unit and means for adding to the count in the summation for each active input of the gate. The summation unit may be either a combinational logic array, operating in parallel or a scanning unit operating sequentially.

Collector-up logic transmission gates

Abstract: Unidirectional and bidirectional bipolar logic transmission gates have an input, an output, a gate control, supply and common terminals. The unilateral transmission gate circuit includes first and second switching transistors and associated first and second source tranisistors. The transistors each have collector, base and emitter electrodes, said first source transistor emitter being connected to said supply terminal. The collector of the first switching transistor is connected to the base of the second switching transistor and defines a gate logic node. The base of the first switching transistor is connected to the first input terminal and the collector of the second switching transistor is connected to the output terminal with both switching transistor emitters being connected to the common terminal. Gate switching means is connected between said gate logic node and said gate control input, said means being responsive to first and second logic levels at said gate control input for driving said gate logic node to first and second states causing the transmission gate to assume open and closed states from input to output. A bidirectional bipolar logic transmission gate includes an additional gate logic node and gate switching means simultaneously drives said gate logic node and additional gate logic node to first and second states causing the transmission gate to assume bilateral open and closed states between said first and second input and output terminals.

Electronically alterable diode logic circuit

Abstract: A crosspoint (X-Y) matrix array of electrically reprogrammable memory logic elements, such as an array of dual dielectric insulated gate field effect transistor (IGFET) structures, is interconnected in a single electrically reprogrammable diode logic array circuit, both for computing the logic function(s) of many variables and for writing and erasing the function(s). Each logic element's high current path is in series with a separate unidirectional diode in order to prevent sneak paths. Electrical access circuitry is also provided for computing the logic function(s) of many variables, each funtion being electrically alterable.

Threshold integrated injection logic

Abstract: Integrated injection logic circuits and semiconductor devices employing threshold functions. Multiple-collector input transistors have their collectors connected to the bases of one or more output transistors. The output transistors have different injection current levels. The switch-ing states of the output transistors are functions of the number of and conduction state of input transistors to which the output transistors are connected and to the weight of the injection current associated with the output transistor.

Logic CMOS transistor circuits

Abstract: The invention relates to logic CMOS transistor circuits formed by at least one gate circuit, each gate circuit comprising a pair of CMOS transistor groups connected in series between the terminals of a power supply. The conductive state of both groups of transistors defines the potential of a common connection point or output node. A power dissipating means of relatively high resistance is coupled in parallel with at least a part of at least one of the said transistor groups, at least during a time interval in which both groups are in a non conductive state. This results in a quasi static behavior of the circuits according to the invention although the basic structure of the same is that of dynamic circuits.

High-speed programmable logic arrays in ESFI SOS technology

Abstract: Exploratory MOS programmable logic array (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated. These PLA's used dynamic logic gates and are built in epitaxial-silicon films on insulators (ESFI) silicon-on-sapphire (SOS) technology. The problems arising with the use of these dynamic gates in a two-stage logic array are discussed and different circuits are presented. The advantage of these circuits, in addition to their high speeds, is reduced power consumption, and the possibility to determine the number of feedback loops when the array is personalized. The features of the circuits are compared with each other with a complete PLA described in an earlier paper (see ibid., vol. SC-10, p.331 (1975)). The results gained from computer simulations agree reasonably well with the experimental results.

Logic gates with forward biased diode load impedences

Abstract: A logic family is provided capable of accomplishing a logic function for each transistor used, i.e., one transistor per logic gate. A plurality of logic gate types are shown, each capable of a different logic function. Nonlinear loads are used in the logic gate circuits.

Regulated power supply with combined series and shunt regulating transistors

Abstract: Unipolar regulated power supplies can be provided with two way control of output voltage by a transistor of polarity opposite to that of the pass transistor connected in shunt with the load and driven from the same error amplifier as the one which drives the pass transistor.

Josephson logic circuit powering arrangement

Abstract: An alternating current powering arrangement for use with Josephson junction devices which have bilateral gain characteristics is disclosed. Using an alternating current input to a Josephson junction logic circuit, it is possible to carry out a desired binary logic function during one half of an alternating current cycle; reset the logic circuit; and carry out a different binary logic function during the second half of the alternating current cycle. In the instance of latching circuits, the Josephson junction logic circuits are reset by the passage of the alternating current (which is normally the gate current of the Josephson junction) through zero every half cycle. In the instance of self-resetting devices, the Josephson junctions normally reset themselves to the zero voltage state. Single phase and multiphase logic circuit powering arrangements are shown including a shift register arrangement which requires only two phases to achieve passage of information from the input to the output of the shift register. All of the arrangements shown include regulating means formed from a string of series connected Josephson junctions, the I-V characteristic of which effectively clips both positive and negative portions of the applied alternating current. Also included is a scheme for powering the logic gates with a constant voltage source and the parallel arrangement thereof which provides stable and isolated logic circuits. Under such circumstances, the maximum value of current applied to the logic circuits is carefully controlled and a plurality of logic circuits may be connected in cascade but isolated from each other across the regulator string. The logic circuits utilized are per se well known and may consist of terminated line logic circuits connected to a pair of low impedance buses via a single current defining resistance or via a pair of current defining resistances of value equal to R/2, where the value of R is large relative to the characteristic impedance of the power buses. Also shown are transformer means for applying AC current from an AC source to a logic circuit via board-to-module, module-to-chip and chip-to-logic circuit transformers.

High Speed MOSFET Circuits Using Advanced Lithography

Abstract: During the last decade we have seen a dramatic increase in the complexity of silicon integrated circuit chips, particularly in memory. The n-channel FET technology is dominant in main memory and in lower performance logic and arrays (i.e., read-only memory and buffers) because of its higher circuit density and simpler processing, whereas bipolar transistor technology dominates for high-performance logic and arrays.

Single bit logic microprocessor

Abstract: A single bit recycling microprocessor which performs sequential and combinational logic equations. The microprocessor has exclusive input and output instructions and performs three basic logic operations, two of which are performed concurrently on each data input. The processor substitutes read only memory (ROM) for a network of logic gates, multiplexers, decoders, flip-flops and counters. The simulation of J-K flip-flops is accomplished by a tandem operation of two R-S flip-flops.

Integrated logic elements with improved speed-power characteristics

Abstract: Transistor logic elements with improved switching speed at a given power. The improvement arises from shunting the current-source transistor in a two-transistor gate by a resistor. The integrated embodiment requires no more area than the conventional structure without the resistor.