Showing papers on "Pass transistor logic published in 1977"

A logic design structure for LSI testability

Abstract: The ability to put hundreds of logic gates on a single chip of silicon offers great potential for reducing power, increasing speed, and reducing cost. Unfortunately, several problems must be solved in order to exploit these advantages of large-scale integration, LSI. This paper will describe a logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI. The design method is based on two concepts that are nearly independent but combine efficiently and effectively. The first is to design sequential logic structures so that correct operation is not dependent on signal rise and fall time or on circuit or wire delay. The second is to design all the internal storage elements (other than memory arrays) so that they can also be operated as shift registers to facilitate testing and diagnostics. Sequential logic, which is difficult to test, can then be transformed to combinational logic, which is less difficult. The transformation is performed during test generation. Advantages and cost impact will also be discussed qualitatively.

GaAs MESFET logic with 4-GHz clock rate

Abstract: Monolithic digital ICs with GaAs MESFETs have been built and operated at clock frequencies up to 4.5 GHz. The fabrication process uses selenium-implanted n-channels and a two-level Cr-Pt-Au metallization with 1-/spl mu/m linewidth and 1-/spl mu/m alignment tolerances. NOR gates with 86-ps propagation delay and 40-mW power consumption have been realized. Binary frequency dividers have been designed with master-slave flip-flops operating from dc up to an average maximum frequency of 4 GHz. In addition, more complex circuits have been integrated on single chips. A general-purpose octal counter with input gating and output buffering and an 8-bit multiplexer/serial data generator exhibit stable and reliable operation.

Threshold I/sup 2/L and its applications to binary symmetric functions and multivalued logic

Abstract: I/SUP 2/L threshold gate using current mirrors providing weighting of inputs, summation, and comparison with a threshold is described and its practical realization is discussed. Application to binary symmetric functions shows significant area savings over standard I/SUP 2/L implementation. A complete multivalued logic family, using a four-level I/SUP 2/L threshold logic technique is introduced.

Inverters and logic gates employing inverters

Abstract: A so-called "programmable inverter" provides either a direct or an inverse signal path between its input and its output depending on a previously applied programming signal which is arranged to cause selective fusing of a fusible link. Such a circuit element may be incorporated in an input or an output of a logic gate so that a single type of gate may be programmed to perform a selected function from a number of functions.

A masterslice LSI for subnanosecond random logic

Abstract: Describes the design and implementation of a bipolar subnanosecond gate arrays with a complexity up to 700 gates. There are three different basic arrays with either 24 or 36 cells or 24 cells plus a 128 bit RAM. Each cell has the logic power of a small MSI. The masterslice is ECL compatible.

Three output level logic circuit

Abstract: A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.

Circuit to improve rise time and/or reduce parasitic power supply spike current in bipolar transistor logic circuits

Abstract: An improvement in output rise time and a reduction in the parasitic power supply strike current is achieved in bipolar transistor logic circuits using an AC coupled feedback circuit. During the low to high transition of the output, an internal voltage is AC coupled to an amplifier which in turn provides a low impedance path at the base of a lower output drive transistor which is coming out of conduction.

Low-temperature f.e.t. for low-power high-speed logic

Abstract: A novel fet cooled to around 100 K is proposed Detailed computer simulations support the conjecture of high-speed switching at low power levels with a power-delay product ≃ 10-14 J

Isoplanar integrated injection logic: a high-performance bipolar technology

Abstract: A newly developed technology is discussed. The emphasis of this approach is on achieving high packing density and high performance by use of various process innovations combined with topological design variations. Factors affecting packing density, DC as well as power delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. The results of computer simulations and measured device parameters and power delay are given. The following gate performance has been obtained at 100-/spl mu/A injector current, /spl beta/u/spl sime/2-4 for all four collectors, speed <10 ns for fan-out of four, speed <5 ns for a fan-out of one. At low currents a speed power product is 0.15 pJ. A packing density of more than 300 gates/mm/SUP 2/ including interconnect and power bussing has been achieved.

Electronic apparatus using complementary MOS transistor dynamic clocked logic circuits

Abstract: An electronic apparatus comprises a timer circuit driven for a given time in response to a key input, complementary MOS transistor clocked dynamic logic circuits each with an output storage capacitance, clock signal supply souce for supplying complementary clock signals to the clocked dynamic logic circuits during the operative period of the timer circuit, and for supplying voltages with fixed levels to the clocked logic circuits during the inoperative period of the timer circuit. During the inoperative period, the output capacitance of the clocked logic circuit is fixed at a fixed potential level. This prevents the simultaneous turning-on of the complementary transistors in a succeeding logic circuit connected to the clocked logic circuits, resulting in little power consumption even when a power switch is not used.

Logic circuit using CMOS transistors

Abstract: A logic circuit using CMOS transistors, in which electrical power is supplied to a CMOS logic circuit that is formed of P-channel type and N-channel type MOS transistors by way of a depletion type MOS transistor. The output level with respect to the voltage of the power source that is used is set at some point by the design of the depletion-type MOS transistor.

Josephson nonlatching logic circuits

Abstract: The authors describe nonlatching logic circuits that can be designed using Josephson junctions as the switching elements. The circuits require no current resetting and can be switched between their two logic states with a subnanosecond delay time. The switching behavior has been simulated numerically. The choice of parameters and junction types is analyzed. The distinctive features which make these circuits attractive are discussed.

Realization of a multivalued integrated injection logic (MI/sup 2/L) full adder

Abstract: A multivalued integrated injection logic scheme and its application to the realization of a full adder is described in this correspondence. The integrated full adder is implemented and fabricated using V-groove isolated I/SUP 2/L technology. Results obtained on the experimental structures indicate that the multivalued full adder offers an increase in functional density while retaining approximately the same area x delay product as a binary full adder at identical power levels.

A charge-balancing monolithic A/D converter

Abstract: The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.

A Josephson logic design employing current-switched junctions

Abstract: A logic scheme using Josephson tunnel junctions in a current-steering mode is described. Switching from voltage V = 0 to V eq 0 is accomplished by adding a fraction of the control-line currents to the bias current. In one form the addition is accomplished by shunting the junction to be switched with a loop containing a second junction serving a diode-like function and causing one or more control lines to possess inductive coupling to the loop. A five-element circuit demonstrating AND, OR and INVERSION operations carried out by this approach has been fabricated and works as expected.

Current mode logic compatible emitter function type logic family

Abstract: An EFL D-type latch having both true and complement output with a data input transistor and a bistable storage cell comprising first and second transistors, at least one of which is multi-emitter, connected such that the true output is connected to the collector of the first transistor of the storage cell and the complement output is connected to the collector of the data input transistor and the second transistor of the storage cell to take advantage of the phase inversion of the latter transistors depending upon which one of these transistors has current flowing therethrough. Also described is an EFL type complement output circuit connected as a D-type master-slave flip-flop, an RS latch, and a JK master-slave flip-flop using an RS master latch and a D-type slave latch. Also disclosed is a toggle flip-flop implemented with a D-type flip-flop to complete an EFL type logic family.

Modular logic circuit utilizing charge-storage transistors

Abstract: The present invention relates to a modular logic circuit, which is preferably utilized in a telephone switching system, comprising electronic logic elements using binary logic operation. The input terminals of the circuit have one input signal at a time applied to them whereupon an output signal is supplied through its output terminals; the output is dependent on how the modular circuit was previously set by electrical means. The logic elements comprise transistors in a matrix arrangement connected to horizontal and vertical lines. The modular circuit of the present invention is characterized in that it can be set any number of times by means of a first setting signal applied to the input terminals and a second setting signal applied simultaneously to the output terminals. The setting signal applied to the input terminals is fed to specified horizontal lines, while the setting signal applied to the output terminals affects at least one vertical line by way of selector switches that connect the output signal path to the output terminals.

C/sup 2/L: A new high-speed high-density bulk CMOS technology

Abstract: C/SUP 2/L, or closed COS/MOS logic, is a new structural approach to high-speed bulk-silicon COS/MOS logic. C/SUP 2/L is a self-aligned silicon-gate CMOS technology where the gate completely surrounds the drain. The use of such geometry maximises the transconductance to capacitance ratio for devices and thus allows high on-chip speed. The CDP 1802 single-chip 8-bit microprocessor, as well as several memory and I/O circuits announced recently by the RCA Solid State Division, are fabricated in this new technology. Generally, C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately 4 times faster than standard CMOS. The fabrication sequence for C/SUP 2/L devices requires 6 photomasks (one less than standard CMOS).

Femtojoule logic circuit using normally-off GaAs m.e.s.f.e.t.s

Abstract: Experimental results are reported on the speed/power performance of normally-off-type GaAs-m.e.s.f.e.t. logic circuits, using an integrated 15-stage ring oscillator as a test circuit. A power consumption as low as 1-5 μW, corresponding to a power-delay product of 1.6 fJ, was obtained. Conversely, a propagation delay time of 650 ps was measured for a power consumption of 20 μW per gate.

Ratioless type MIS logic circuit

Abstract: A ratioless type MIS logic circuit comprises a logic block including at least one depletion mode FET inherently having a gate-to-source parasitic capacitance and a gate-to-drain parasitic capacitance, an output capacitance, a circuit for precharging the output capacitance and depletion mode clamping FETs connected one with each of the two ends of the logic block, the clamping FETs having their gates connected with a reference potential and the threshold voltage value of the FET in the logic block being larger than those of the clamping FETs.

Some considerations on high-speed injection logic

Abstract: After a brief review of the factors that limit the switching speed of standard I/SUP 2/L, the propagation delay time of some special high-speed I/SUP 2/L gates is computed. For a gate realized in oxide-isolated, shallow epitaxial layers, the delay time is directly dependent on the injector base width. Generally, the n-p-n switching transistor hardly contributes to the time delay. For a modified I/SUP 2/L gate in which saturation of the injector is avoided, the delay time is mainly determined by the unity gain frequency of the switching transistor. However, due to the heavy saturation of this transistor, values of /spl tau//SUB d/ already realized indicate that the speed improvement is less than an order of magnitude.

Improved feedback ECL gate with low delay-power product for the subnanosecond region

Abstract: Feedback ECL gates are well suited as basic elements for high-speed LSI circuits. Unfortunately for higher voltage swings, they have a hysteresis which reduces the noise immunity. Here it will be demonstrated theoretically how to remove the hysteresis and how to optimize the transfer characteristic using emitter resistors. For such a gate, a power dissipation of 1.6 mW and a propagation delay time of less than 0.6 ns are evaluated by simulation using the parameters of today's available technologies.

Safety test circuit for combustion control apparatus

Abstract: A safety test circuit for a combustion control apparatus. This safety test circuit is used to check the off-failure of a safety transistor actuating a safety relay which acts to stop the operation of controlled units in the event of mal-combustion or the like, and also to check the on-failure of a control transistor actuating a control relay which controls the controlled units. An operation instruction signal and the collector potential of the safety transistor are applied to a logic circuit including a flip-flop and logic gates so that the off-failure of the safety transistor can be driven to check, utilizing the electrical signal propagation delay time of the elements constituting the logic circuit, before the propagation delay time has elapsed. The logic circuit is also used for similarly checking the on-failure of the control transistor. A check signal may be additionally applied to the logic circuit so that these transistors can be tested during the continuous operation of the combustion control apparatus.

Integrated logic - Static induction transistor logic

Abstract: SOLID-STATE CIRCUITS are designed to minimize both delay time and operational power. The product of these is thought t o be constant, represented by a specific figure for each type of integrated circuit. The 12L structure has been shown to operate with the lowest switching energy’. The power efficiency of the Vertical Injection Logic (VIL) structure shows a further improvement, by a factor of two. However, its fabrication requires the use of 7-8 masks’. A new logic circuit structure is proposed Static Induction Transistor Logic (SITL) utilizing the static induction transistor ( SIT)3. This logic circuit permits a further reduction in the power-delay time product (theoretically 6 x and experimentally, one order of magnitude). In the case of 12L, it is made by a 3 or 4-mask technology. The packing density can be as high as 1000 gates/cm2. In this logic structure, the SITS are used as the output transistors and the lateral bipolar PNP transistor is used as the injector, as usual, as shown in Figure 1. The SIT consists of Nt drains on the top surface of the Nepitaxial layer, a Pt gate configured on both sides of the drain on the same surface and the space charge layer formed surrounding the drain regions, Nchannels penetrating the gate region below the drains and the N+ source substrate. The channels are about 2-3 p m in diamcter and are formed by lateral P-type diffusion. The fabrication process in this case is as follows. The Nepitaxial layer is grown on the N+ substrate, having a carrier concentration of 2-3 x 1013 cm-3 and a thickness of 4-5 pm. After oxidation and photolithography, B-diffused layers were formed as the gate regions of the SIT and the emitter of the injector (the lateral transistor), followed by the second oxidation. Then, the Nf -diffusion layers are formed as drain regions, followed by the opening of contact holes in the Si02 film, using the third photolithography. After A1 evaporation, the A1 film is selectively etched, and the ring oscillator formed, as shown in Figure 2.

a monograph on ternary threshold logic

Abstract: Publisher Summary This chapter focuses on ternary threshold logic. Multiple-valued logic has provided an alternative that was theoretically available since the beginning of the century but whose circuit implementations have developed in the last decade. Threshold logic allows working with high levels of information per gate. The devices for threshold logic implementations were of the magnetic type; however, with the advances made in active circuits synthesis and integrated circuit technology, semiconductor implementations were reported. Whenever a ternary function is a threshold function, it is convenient to implement it by means of a threshold gate. A threshold gate, whose threshold may be controlled, provides a whole family of threshold functions; a new scheme of logic design appears, where the variables are the threshold values and/or the input vectors.

An experimental system for power/timing optimization of LSI chips

Abstract: An experimental system of programs is described which places logic gates on a chip, globally wires the gates and then optimizes the power required to drive them. Further power reductions are realized by using power-oriented placement improvement techniques. A companion paper describes how the optimization is accomplished by using the timing requirements of the chip as constraints and assigning delays to the logic gates so that these constraints are met and the power is minimized.

Logic transition circuits

Abstract: Transition circuits are provided for interfacing logic gate circuits from different kinds of logic gate families where the characteristic logic state voltage levels differ between the families as do the separations between these logic state voltage levels as they occur in these logic families.

Logic circuits incorporating a dual function input

Abstract: A dual function capability is incorporated into one input of an emitter coupled logic gate to allow a user to selectively enable the logic circuit to operate in a multifunction mode. The dual function input can recognize both normal binary voltage levels and operate as a conventional input for digital information, and also recognize voltage levels not within the normal binary voltage levels and modify the circuit function correspondingly.

Condition control system utilizing digital logic

Abstract: A condition control system which utilizes digital logic to respond to the state of the condition being sensed. The control system utilizes a condition responsive element that is energized from an alternating current source and controls a first alternating current type of amplifier. The output of the amplifier is compared with a periodically generated pulse or logic command in an S-R latch circuit which is made up of a pair of NAND gates in a cross-connected configuration. The digital logic is arranged so that an output transistor and relay are energized only when the system senses the presence of the desired condition thereby indicating that it is safe to energize associated equipment.

Self-adjusting compatibility circuit for digital to analog converter

Abstract: A circuit for interfacing a digital to analog converter with input signals from three different logic systems, whereby appropriate threshold switching signals compatible with each logic system are presented to the converter when the proper logic control signal is applied to the circuit. The first logic system is characterized by logic control signals within a first voltage range, and switching thresholds which differ from the logic control signals by a fixed increment; the second system by logic control signals within a second voltage range higher than the first range, and switching thresholds equal to a fixed proportion of the logic control signal; and the third system by a substantially constant switching threshold for a predetermined positive supply voltage level.