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Showing papers on "Pass transistor logic published in 1978"


Journal ArticleDOI
TL;DR: This paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements that provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.
Abstract: This paper addresses the simulation and detection of logic faults in CMOS integrated circuits. CMOS logic gates are intrinsically tri-state devices: output low, output high, or output open. This third, high-impedance condition introduces a new, nonclassical logic fault: the “stuck-open.” The paper describes the modeling of this fault and its complement, the stuck-on, by means of gate-level networks. In addition, this paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements. The models are gate-level in structure, provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.

618 citations


Journal ArticleDOI
Abstract: An integrated inverter stage operating in the gigabit range at a static power dissipation of 100 µW was built for future use in LSI logic circuits. Planar gallium arsenide technology was employed using selective ion-implanted enhancement mode junction field-effect transistors (E-JFET) having 3-µm gate lengths. A nine-stage ring oscillator served as a test vehicle to assess the speed-power product for digital applications. A theoretical analysis shows the transistor operates during the switching transient in the saturation regime, notwithstanding steady-state operation in the linear regime. When the transistor is switched off, the transient response is governed by the load resistance and the input capacitance of the subsequent stage. Means of reducing the switching time by increasing the supply voltage, nonlinear load devices, an output buffer stage, and reduction of gate length and width are described. Directly coupled E-JFET logic does not require level shifting, and, therefore, offers advantages over depletion-mode gallium arsenide MESFET logic by reducing the number of circuit elements per gate. Projected gallium arsenide E-JFET LSI logic circuits will surpass silicon-based bipolar logic with respect to both speed and power, and n-channel silicon MOS logic with respect to speed.

92 citations


Journal ArticleDOI
TL;DR: Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage with an AC power supply in a latching mode with a reset capability consistent with a machine cycle time less than 5 ns.
Abstract: Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage. The gates operated with an AC power supply in a latching mode with a reset capability consistent with a machine cycle time less than 5 ns. OR, AND, and INVERT functions and fanout capability were demonstrated. Dissipation per gate was about 2.0 /spl mu/W.

38 citations


Patent
Allan A. Alaspa1
21 Dec 1978
TL;DR: In this article, a CMOS logic circuit with a basic CMOS shift register useful as a shift register or in sequential logic circuits is provided, where the use of a single input clock signal along with the reduced number of transistors is achieved by proper selection of threshold voltages of the transistors.
Abstract: A CMOS logic circuit having a basic CMOS shift register useful as a shift register or in sequential logic circuits is provided. The circuit has two inverters plus an output inverter and two transistors which are enabled by a clock signal to couple the inverters together. The use of a single input clock signal along with the reduced number of transistors is achieved by proper selection of threshold voltages of the transistors.

37 citations


Patent
30 Jun 1978
TL;DR: In this article, an arithmetic logic unit bit-slice implemented as an integrated circuit is able to perform iterative algorithms such as multiply and divide, using control logic which is also part of the integrated circuit to cause the selected algorithm to be performed.
Abstract: An arithmetic logic unit bit-slice implemented as an integrated circuit is able to perform iterative algorithms such as multiply and divide, using control logic which is also part of the integrated circuit to cause the selected algorithm to be performed. A plurality of the arithmetic logic unit bit-slices may be concatenated to provide the word size desired. The bit-slices are electrically identified as the most significant, least significant, and middle digits, such identification being provided to the control logic so that the control logic is identical on each bit-slice irresepective of its position within a word to enable the control logic to cause performance of the algorithms for any desired word length.

28 citations


Proceedings ArticleDOI
01 Jan 1978
TL;DR: A method was derived which could algebraically detect all logic hazards contained in combinational switching circuits by means of the canonical forms of the B-ternary logic functions realized by the circuits.
Abstract: Both the steady states and some transient states of switching circuits can be described by B-ternary logic in which the truth values 0, 1 and 1/2 are used respectively to represent false, true and uncertainty. This paper showed the methods of detecting and identifying various kinds of static hazards contained in combinational switching circuits by means of the canonical forms of the B-ternary logic functions realized by the circuits. Particularly, a method was derived which could algebraically detect all logic hazards contained in the circuits. It was also pointed out that there were some dynamic hazards which were detectable by B-ternary logic.

24 citations


Patent
24 Jul 1978
TL;DR: In this article, the authors describe a multi-function logic circuit which simultaneously receives data signals and control signals, and output logic signals, representing the result of the selected logical operation, are generated by the circuits.
Abstract: Disclosed are multi-function logic circuits which simultaneously receive data signals and control signals. The control signals select logic operations for the multi-function logic circuits to perform on the data signals. Output logic signals, representing the result of the selected logical operation, are generated by the circuits. A four transistor embodiment selectively performs an EXCLUSIVE OR, OR, and NAND operation. A six transistor embodiment selectively performs a FULL ADD, NOR, OR NAND, and AND operation. The six transistor embodiment is suitable for use as an arithmetic logic unit in a digital computer.

22 citations


Patent
17 Apr 1978
TL;DR: In this article, the authors propose a logic circuitry with a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs, at least one output device is connected to two or more input devices.
Abstract: Logic circuitry provides predetermined logic outputs in response to logical combinations of inputs. The circuitry includes a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs. At least one output device is connected to two or more input devices. Means having predetermined logic levels is provided connected intermediate the input and output devices for controlling the conduction state of the output devices as a function of the input devices and the predetermined logic levels.

20 citations


Proceedings ArticleDOI
19 Jun 1978
TL;DR: The outline and the experimental results of the system which automatically restructures and partitions a logic circuit consisting of standard SSI's and MSI's so that the gate types and the numbers of input/output terminals of the reorganized circuits are within the restrictions of the specified LSI are described.
Abstract: Described is the outline and the experimental results of the system which automatically restructures and partitions a logic circuit consisting of standard SSI's and MSI's so that the gate types and the numbers of input/output terminals of the reorganized circuits are within the restrictions of the specified LSI.

14 citations


Patent
05 Apr 1978
TL;DR: In this article, the authors used the period of oscillation of a charge-flow transistor as a measure of an environmental condition, which can be used as a measurement of environmental conditions.
Abstract: Oscillators that include charge-flow transistor logic elements, each logic element including a charge-flow transistor and a load element, in combination. The charge-flow transistors have TURN-ON times t on and TURN-OFF times t off that can be very different from one another (e.g., t on can range from milliseconds to hundreds of seconds; whereas in the charge-flow transistors shown herein t off is typically less than one microsecond). The magnitude of t on is sensitive to the environment; hence, the period of oscillation can be used as a measure of an environmental condition.

14 citations


Proceedings ArticleDOI
01 Jan 1978
TL;DR: I 2 L circuits for the various gate types and design approaches that have been proposed, including some memory elements, are suggested, and some of the problems of using I 2 L multiple-valued logic chips in practical designs are discussed.
Abstract: While various integrated circuit technologies have been proposed for multiple-valued logic, it appears that for the near future current-mode integrated injection logic (I2L) will predominate. The present paper suggests I2L circuits for the various gate types and design approaches that have been proposed, including some memory elements, and discusses some of the problems of using I2L multiple-valued logic chips in practical designs.

Patent
02 Feb 1978
TL;DR: In this article, a field effect transistor and first and second logic performing diodes are interconnected with one another so as to reduce the number of circuit components and to increase the operating speed relative to conventional logic circuits.
Abstract: Compact and high speed logic circuits that utilize CMOS technology to perform the Boolean operations A·B and A+B. The presently disclosed logic circuits are comprised of a field effect transistor and first and second logic performing diodes which are uniquely interconnected with one another so as to reduce the number of circuit components and to increase the operating speed relative to conventional logic circuits.

Patent
30 Mar 1978
TL;DR: In this article, a current regulator for a pulse code modulated (PCM) transmission line is interposed between a voltage potential and a load for limiting the current flow to the load.
Abstract: A current regulator for a pulse code modulated (PCM) transmission line is interposed between a voltage potential and a load (consisting of repeater amplifiers along the PCM transmission line) for limiting the current flow to the load. During normal operation, the regulator provides a relatively low impedance path from the voltage potential to the load through a series pass transistor and a sensing resistor. During an overload condition, which is sensed by the sensing resistor, the series pass transistor is deprived of base drive thereby providing a high impedance path with an accompanying increased voltage drop across the series pass transistor of the series regulator. This voltage drop is used to drive a timer which turns the series pass transistor off and on, with a low on time or duty cycle, in order to minimize power dissipation during the overload condition. After the overload condition has been alleviated, the series pass transistor is turned back on by the timer, and due to the low current flowing to the load, the series pass transistor is again returned to its relatively low impedance conducting condition.

Patent
09 Jan 1978
TL;DR: In this article, an integrated logic circuit includes an array of insulated gate field effect transistors formed at the crossings of a plurality of substantially parallel first conductor tracks and strip-shaped surface regions.
Abstract: An integrated logic circuit includes an array of insulated gate field effect transistors formed at the crossings of a plurality of substantially parallel first conductor tracks which form the transistor gate electrodes and a plurality of substantially parallel strip-shaped surface regions which form the source and drain electrode regions of the transistors. The field effect transistors of the device include a first group of transistors having a first threshold voltage and a second group of transistors having a second threshold voltage different from the first. In order to make a more compact, easily-designed and easily-manufactured circuit, the conductor tracks and the strip-shaped surface regions form a nonuniform array in which the track and surface regions need not all be of the same length. Further efficiencies are achieved by branching the strip-shaped surface regions where appropriate to implement the desired logic combination.

Patent
08 Jun 1978
TL;DR: In this paper, a collector of a transistor for a level-converter which converts a signal level from an upper layer or first logic level to a lower layer or second logic level is connected to a gate (or a base) of a driving transistor placed in the lower layer through a current limiting element integrated on the same chip to effectively use an injection current in a signal-level converting circuit used in a static induction transistor logic or in an integrated injection logic which is constructed by using a laminated circuit construction.
Abstract: In a Static Induction Transistor Logic (or an Integrated Injection Logic) semiconductor device having a lateral PNP transistor used as an injector and a longitudinal field effect transistor (or a longitudinal NPN transistor) used as a driving transistor, a collector of a transistor for a level-converter which converts a signal level from an upper layer or first logic level to a lower layer or second logic level is connected to a gate (or a base) of a driving transistor placed in the lower layer through a current limiting element integrated on the same chip to effectively use an injection current in a signal-level converting circuit used in a Static Induction Transistor Logic or in an Integrated Injection Logic which is constructed by using a laminated circuit construction.

Patent
15 Aug 1978
TL;DR: In this paper, the disclosed logic circuit includes one transistor and a plurality of Schottky barrier diodes in each logic circuit "cell", with the plurality of such cells being interconnected to perform desired logic functions.
Abstract: HIGH DENSITY INTEGRATED LOGIC CIRCUIT Abstract Of The Disclosure The disclosed logic circuit includes one transistor and a plurality of Schottky barrier diodes in each logic circuit "cell", a plurality of such cells being interconnected to perform desired logic functions. Cell interconnections are made by interconnecting metallurgy which can have a rela-tively high resistance with relatively long interconnecting paths between a sending circuit cell and a receiving circuit cell. The undesirable effects of this metallurgy resistance are overcome by driving the base of the receiving transistor through a base drive resistor in the sending cell.

Proceedings ArticleDOI
E. Blaser1, D. Conrad
01 Jan 1978
TL;DR: A FET logic configuration that uses both enhancement-mode and depletion-mode devices in a single-input, multiple-output logic circuit, will be covered, citing improvement of power-delay product by a factor of four.
Abstract: A FET logic configuration that uses both enhancement-mode and depletion-mode devices in a single-input, multiple-output logic circuit, will be covered, citing improvement of power-delay product by a factor of four.

Patent
24 Apr 1978
TL;DR: In this paper, an integrated logic circuit arrangement consisting of an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and gate held at a reference potential, is presented.
Abstract: An integrated logic circuit arrangement comprising: an input junction field effect transistor having at least one source for receiving a digital input signal, a drain to which a load is connected, and gate held at a reference potential, said junction field effect transistor being operative to effect switching operation in accordance with said digital input signal; and an output bipolar type transistor having its base connected to said drain to effect switching operation in accordance with an output signal delivered from said drain. This integrated logic circuit arrangement provides high speed logic operation, low power dissipation and high integration density.

Journal ArticleDOI
TL;DR: In this paper, the design of three-valued cycling gates with c.m.o.s. integrated circuits is presented, and the circuits for the cycling and the inverse cycling gates prove to be simpler than those previously reported.
Abstract: The design of three-valued cycling gates with c.m.o.s. integrated circuits is presented. Circuits for the cycling and the inverse cycling gates prove to be simpler than those previously reported.

Patent
Yuzo Usui1
08 Dec 1978
TL;DR: In this paper, a delay element is introduced into a transistor-transistor logic circuit having a totem-pole-connected inverter transistor and an off-buffer transistor, in order to ensure a safe and correct operation even in the case where the transistor transistor is used as an element of multiple-connected transistor transistors.
Abstract: A delay element is introduced into a transistor-transistor logic circuit having a totem-pole-connected inverter transistor and an off-buffer transistor, in order to ensure a safe and correct operation even in the case where the transistor-transistor logic circuit is used as an element of multiple-connected transistor-transistor logic circuits.

Patent
25 Sep 1978
TL;DR: In this paper, an extremely fast, highly regulated and non-resistive semiconductor digital logic inverter gate which is suitable for use as a fundamental building block in an uncommitted gate array is presented.
Abstract: An extremely fast, highly regulated and nonresistive semiconductor digital logic inverter gate which is suitable for use as a fundamental building block in an uncommitted gate array includes an input conductor, at least one output conductor, a first current source providing a fixed current of a given magnitude to the input conductor, a second current source providing a current varying exponentially with input voltage to each output conductor, and a current control circuit operating in response to current flow through the input conductor to control the magnitude of current provided by the second source of current to each of the output conductors at a magnitude greater than the first magnitude or at a nonzero magnitude substantially less than the first magnitude. Subnanosecond time delays in switching between digital logic states are attained by constructing the logic gate as an integrated circuit from Schottky diodes which have very little transit time delay and bipolar transistors which are never biased into either saturation or cutoff. Capacitance charging time is minimized by utilizing a small difference in forward bias voltage drops across different kinds of Schottky diodes to clamp digital logic voltage swings at approximately 133 millivolts or less. Because of its exponential voltage current relationship this voltage differential applied across the base emitter terminals of a transistor utilized in the second current source is sufficient to provide current differentials greater than 100:1 for maintenance of a good noise margin.

Proceedings ArticleDOI
Ronald W. Knepper1
01 Jan 1978
TL;DR: The dynamic use of depletion-mode devices resulting in improved performance in MOSFET enhancement/depletion circuits and the method - DDM - applies to the design of logic, memory and driver circuits.
Abstract: This paper will describe the dynamic use of depletion-mode devices resulting in improved performance in MOSFET enhancement/depletion circuits. The method - DDM - applies to the design of logic, memory and driver circuits.

Proceedings ArticleDOI
Paul M. Solomon1
01 Jan 1978
TL;DR: In this article, the theoretical performance of GaAs MESFET logic gates and attempts to obtain a realistic comparison of GAAs vs Si devices under typical loading conditions imposed by large random logic arrays.
Abstract: This paper examines the theoretical performance of GaAs MESFET logic gates and attempts to obtain a realistic comparison of GaAs vs Si devices under typical loading conditions imposed by large random logic arrays. GaAs was found to have a speed advantage of 3-6 over Si, depending on the operating voltage. Normally off type MESFET devices were attractive at gate lengths of 0.5µm, giving loaded delays of 105ps. Logic swings were 600mV requiring a threshold voltage control of ±50mV.

Proceedings ArticleDOI
A. Yiannoulos1
01 Jan 1978
TL;DR: A vertically structured I2L gate, integrated with linear SBC processing, will be discussed, demonstrating second generation I-2-L performance with unrestrained SBC capability.
Abstract: A vertically structured I2L gate, integrated with linear SBC processing, will be discussed. Previous (standard I2L) logic/linear function conflicts stemming from structural constraints have been reconciled, demonstrating second generation I2L performance with unrestrained SBC capability.

Proceedings ArticleDOI
10 Apr 1978
TL;DR: In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementation are compared to their binary full adder network counter equivalents.
Abstract: Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementation are compared to their binary full adder network counter equivalents. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over fifty percent savings in the total number of signal variables required to implement the parallel counter results. With the circuits we describe here, fifty percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters.

Patent
11 Sep 1978
TL;DR: In this paper, logic level shifting circuits are described in which integrated circuits process binary logic input signals of logic levels different from the input logic levels of the integrated circuits but within the ranges of tolerance and safety of said integrated circuits.
Abstract: Logic level shifting circuits are described in which integrated circuits process binary logic input signals of logic levels different from the input logic levels of said integrated circuits but within the ranges of tolerance and safety of said integrated circuits. Such logic level shifting techniques are used as a simple but effective method to cut down power consumption in luminous displays using seven-segment LED's or the like which may be placed in series as a result of logic level shifting between the respective counters and decoders which control them.

Patent
Stanley E. Schuster1
30 Jun 1978
TL;DR: In this paper, a push-pull driver circuit is proposed to turn on one of two transistors mounted in series and the inversion of that signal is applied to the second transistor in the series path and the output taken from between them operates to isolate the load.
Abstract: A push-pull driver circuit wherein the input signals is applied to turn on one of two transistors mounted in series and the inversion of that signal is applied to the second transistor in the series path and the output taken from between them operates to isolate the load and since one and only one of the two transistors in the series path is conducting there is a path to charge and discharge the load capacitance but no path through both devices for power dissipation. The driver circuit can be built into a 2-bit partitioning circuit which in turn, when used with a programmed logic array and the relative capacitance of the various parts being isolated from each other by a coupling circuit, the resulting assembly provides a high performance programmed array logic device.

Proceedings ArticleDOI
03 Apr 1978
TL;DR: This paper will explore recent advances in the design of sequential circuits using self-checking alternating logic, which is based on the successive execution of a function and its dual.
Abstract: There has been considerable study of the tradeoff between improved reliability and additional hardware. An alternative is to trade speed for improved reliability, as in alternating logic, which is based on the successive execution of a function and its dual. In addition to doubling time, this approach involves an increase in hardware which, however, is generally modest compared to the usual hardware redundancy approaches. This paper will explore recent advances in the design of sequential circuits using self-checking alternating logic.

Proceedings ArticleDOI
M. Klein1, D. Herrell, A. Davidson
01 Jan 1978
TL;DR: In this article, experimental Josephson interferometer logic gates fabricated in a 5 μm technology with 1 μW/gate dissipation were presented, with measured delays of 40, 95 and 120ps for OR, AND and master slave latch, respectively.
Abstract: This paper will cover experimental Josephson interferometer logic gates fabricated in a 5 μm technology with 1 μW/gate dissipation, citing measured delays of 40, 95 and 120ps for OR, AND and master slave latch, respectively.

Proceedings ArticleDOI
01 Jan 1978
TL;DR: A philosophy for implementation of three-value logic is introduced utilizing the tri-state concept found in conventional T2L buffers, whereby a three-valued logic family can be constructed by utilizing the high impedance state as a distinct logic input as well as output.
Abstract: A philosophy for implementation of three-value logic is introduced utilizing the tri-state concept found in conventional T2L buffers. By utilizing the high impedance state as a distinct logic input as well as output, a three-valued logic family can be constructed. Circuits that realize one functionally complete set of three-valued functions are described. The circuits are basically T2L in nature, and retain many of the desirable properties of that family. One supply is required, and no level conversion circuitry is necessary to interface between the tri-state circuits and conventional binary T2L.