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Showing papers on "Pass transistor logic published in 1983"


Journal ArticleDOI
TL;DR: A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.
Abstract: Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.

309 citations


Journal ArticleDOI
TL;DR: An optical logic array processor is constructed that can implement parallel operations of addition or subtraction for two binary variables without considering the carry mechanism, and it is shown that the proposed method can be applied to combinational circuits.
Abstract: On the basis of a lensless shadow-casting technique, a new, simple method of optically implementing digital logic gates has been developed. These gates are capable of performing a complete set of logical operations on a large array of binary variables in parallel, i.e., the pattern logics. A light-emitting diode (LED) array is used as an incoherent light source in the lensless shadow-casting system. Sixteen possible functions of two binary variables are simply realizable with these gates in parallel by controlling the switching modes of the LED’s. Experimental results demonstrate the feasibility of various gate arrays, such as AND, OR, NOR, XOR, and NAND. As an example of application of the proposed method, we construct an optical logic array processor that can implement parallel operations of addition or subtraction for two binary variables without considering the carry mechanism. Use of the light-modulated LED array means that the proposed method can be applied to combinational circuits.

223 citations


Journal ArticleDOI
TL;DR: It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin of logic circuits, and the formal equivalence of four criteria for this worst- Case Static noise margin is demonstrated.
Abstract: Various criteria have been formulated in the past for analytically calculating the worst-case static noise margins of logic circuits. Some of these criteria are based on infinitely long chains of gates, others on flip-flop circuits. It is shown that the flip-flop approach is equivalent to an infinitely long chain with respect to the worst-case static noise margin. Furthermore, the formal equivalence of four criteria for this worst-case static noise margin is demonstrated. Additionally, a method for computer simulation is discussed.

218 citations


Proceedings ArticleDOI
27 Jun 1983
TL;DR: An application of the D-algorithm in generating tests for MOS circuit faults is described, which includes modeling and test generation for combinational and acyclic MOS circuits that may contain transmission gates and buses.
Abstract: An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both, the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

142 citations


Patent
09 May 1983
TL;DR: Pass transistors as mentioned in this paper are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node.
Abstract: PASS transistors are used to reduce the layout complexity of logic circuits by using PASS transistors connected to pass a first and second input function to an output node in response to selected CONTROL signals, thereby to generate a selected output function on the output node. The PASS transistor comprises a transistor capable of passing an input function in response to a CONTROL signal applied to the transistor thereby to generate an output function related to the input function. In general, the input function comprises less than all of a set of input variables and the CONTROL function comprises one or more of the remainder of the set of input variables.

117 citations


Proceedings ArticleDOI
27 Jun 1983
TL;DR: A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.
Abstract: This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.

88 citations


Patent
Kenji Ohmori1
18 Jul 1983
TL;DR: In this article, a gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof, and a decode memory is preliminarily loaded with decoding patterns.
Abstract: A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets which are preliminarily decided for each gate as regards a logic signal pair of each logic group input signal. In a gate memory unit (25), the variable pair is subjected to a logic operation decided for the gate to provide a logic signal of the logic group output signal. At first, a register set (15) is loaded with an input signal of the assembly. Later, the register set is loaded with the output signal of each logic group, which output signal is used in a next succeeding step as the input signal of another logic group. Preferably, each logic group input signal is given by eight logic signals. In this event, each logic signal may be given as a permutation of logic one and/or zero states, sixteen in number.

39 citations


Patent
17 Oct 1983
TL;DR: A universal logic circuit as mentioned in this paper performs a selected one of several logic operations on a pair of input signals in response to the receipt of a control signal and the terminals to which the input signals and control signal are coupled.
Abstract: A universal logic circuit that performs a selected one of several logic operations on a pair of input signals in response to the receipt of a control signal and the terminals to which the input signals and control signal are coupled

38 citations


Patent
Charles Meng-Yuan Lee1
23 Dec 1983
TL;DR: In this paper, a complementary MOS static EXCLUSIVE OR gate is formed by a PMOS logic network having a pair of cross-coupled PMOS transistors and an NMOS logic networks having two parallel branches.
Abstract: A complementary MOS static EXCLUSIVE OR gate is formed by a PMOS logic network having a pair of cross-coupled PMOS transistors and an NMOS logic network having two parallel branches, each of the branches containing a separate pair of NMOS transistors connected in series.

36 citations


Journal ArticleDOI
Z.E. Skokan1
TL;DR: The PLM is a single mask, programmable cell array with complete interconnect that achieves subnanosecond cell delay and 400-gate complexity with less than 1 W of power, and it is fabricated through a low-density process resulting in low cost and a four-day turnaround.
Abstract: The PLM is a single mask, programmable cell array with complete interconnect. It is 100% wireable and 100% testable with built-in LSSD, it achieves subnanosecond cell delay and 400-gate complexity with less than 1 W of power, and it is fabricated through a low-density process resulting in low cost and a four-day turnaround. This paper describes why the PLM was developed, its operational characteristics, and how it differs from conventional gate arrays.

32 citations


Patent
23 Mar 1983
TL;DR: In this article, a functional testing system for programmable logic devices is presented, where test vectors are generated by a shift register and applied to the contact pins of the logic device through isolation elements so that all pins may be treated alike regardless of whether they are inputs or outputs.
Abstract: A functional testing system for programmable logic devices. Test vectors are generated by a shift register and applied to the contact pins of the logic device through isolation elements so that all pins may be treated alike regardless of whether they are inputs or outputs. The logic level on pins that are outputs are controlled by the logic device, while logic levels on pins that are inputs are controlled by the shift register. The response of the logic device to the test vector is recorded in an output shift register and the response is then shifted out of the shift register to one input of an exclusive OR gate that also receives outputs from predetermined stages of the test vector shift register to create a pseudo-random function. The output of the exclusive OR gate is shifted into the test vector shift register as each bit of the logic device's response is applied to the exclusive OR gate thereby creating a new test vector. The number of test vectors applied to the logic device is counted and when a predetermined number is reached, the test terminates and the current test vector is then stored and compared to the final test vector obtained by performing the same test on an identical circuit known to be operating correctly. The testing system thus evaluates the functionality of the logic device while also providing the stimulus to the device.

Patent
25 Jan 1983
TL;DR: In this article, a CMOS logic input circuit comprises two complementary transistor pairs, TR1 and TR2; TR3 and TR4 coupled in series between the supply rails, such that the switching threshold is substantially independent of transistor characteristics.
Abstract: A CMOS logic input circuit comprises two complementary transistor pairs, TR1 and TR2; TR3 and TR4 coupled in series between the supply rails. The gates of n-channel transistor TR4 and p-channel transistor TR1 are coupled to the positive and negative supply rails respectively. A switching function is performed by TR2 and TR3. The arrangement is such that the switching threshold is substantially independent of transistor characteristics.

Journal ArticleDOI
T. Tokuda1, K. Okazaki, K. Sakashita, I. Ohkura, T. Enomoto 
TL;DR: The new timing verification method using the delay model is evaluated with respect to delay-time accuracy and execusion time in a logic LSI and circuit simulator accuracy is obtained in the short computer run time of a logic simulator.
Abstract: The propagation delay time of the ED MOS logic gate is precisely analyzed considering input waveform and loading conditions. According to theoretical consideration and circuit analysis, the rise mode delay time tpLH is approximated as a function of the output capacitance of only the gate concerned. The fall mode delay time t.pHL is determined by the input capacitance and output capacitance of the gate concerned. These results allow the easy implementation of the delay model into a logic simulator. A precise delay simulation is attained by considering the delay components, corresponding to each input node, at the output side of the logic element. The propagation delay times of the transmission gate are precisely analyzed. The operations of the transmission gate are divided into two modes; synchronous mode and asynchronous mode. Corresponding to each mode, the transmission gate, the preceding gate, and the succeeding gate have two kinds of delay times. To simulate delay times of each gate precisely, models which treat these three logic elements as one primitive element in a logic simulator have been proposed. The new timing verification method using the delay model is evaluated with respect to delay-time accuracy and execusion time in a logic LSI. Through this method, circuit simulator accuracy is obtained in the short computer run time of a logic simulator.

Patent
22 Jun 1983
TL;DR: In this paper, a plurality of logic gates having common data inputs are selected by activation and deactivation of switches connecting the logic gates to circuit power terminals, and a buffer inverter is added to each logic gate output whose power leads are connected to the circuit power terminal as are the logic gate.
Abstract: A plurality of logic gates having common data inputs are selected by activation and deactivation of switches connecting the logic gates to circuit power terminals. In one embodiment both power leads of the logic gate are connected by two power switches to two circuit power terminals. In a second embodiment, the first power lead of the logic gate is continuously connected to the first circuit power terminal and the second gate power lead is connected to the second circuit power terminal by a first power switch for a select and to the first circuit power terminal by a second power switch for a deselect. The second embodiment includes a buffer inverter on each logic gate output whose power leads are connected to the circuit power terminals as are the logic gates. Alternatively, the second switch could connect the input of the inverter to the first circuit power terminal for a deselect.

Journal ArticleDOI
TL;DR: In modern high-speed systems, avoid wire-OR logic in transmission lines whenever possible or make allowances for its foibles.
Abstract: In modern high-speed systems, avoid wire-OR logic in transmission lines whenever possible or make allowances for its foibles.

Patent
06 Oct 1983
TL;DR: Universal logic circuit cells as discussed by the authors provide AND and OR on other logical functions on input signals and include a conventional AND or OR gate, or other logic gate, and associated input and output connections and circuitry that enables them to be used in many applications.
Abstract: Universal logic circuit cells for use in designing and laying out electronic circuits. The cells provide AND and OR on other logical functions on input signals, and include a conventional AND or OR gate, or other logic gate, and associated input and output connections and circuitry that enables them to be used in many applications. The cells simplify laying out a combinatorial logic circuit after it has been designed.

Proceedings ArticleDOI
J. Tanida1, Y. Ichioka1
15 Apr 1983
TL;DR: Parallel computation structures of the developed optical digital array processor are demonstrated by implementing pattern logics for two binary images with high space-bandwidth product.
Abstract: A simple method for optically implementing digital logic gates in parallel has been developed. Parallel logic gates can be achieved by using a lensless shadow-casting system with a light emitting diode array as an incoherent light source. All the sixteen logic functions for two binary variables, which are the fundamental computations of Boolean algebra, can be simply realized in parallel with these gates by changing the switching modes of a LED array. Parallel computation structures of the developed optical digital array processor are demonstrated by implementing pattern logics for two binary images with high space-bandwidth product. Applications of the proposed method to parallel shift operation of the image, differentia-tion, and processing of gray-level image are shown.

Patent
Charles Meng-Yuan Lee1
23 Dec 1983
TL;DR: A dynamic CMOS logic circuit for computing multiple AND functions contains a sequence of at least three successive stages controlled by the same timing signal, each stage having a logic network of driver transistors in which at most three such transistors are connected in series along any path through the network.
Abstract: A dynamic CMOS logic circuit for computing multiple AND functions contains a sequence of at least three successive stages controlled by the same timing signal, each stage having a logic network of driver transistors in which at most three such transistors are connected in series along any path through the network.

Patent
Byron G. Bynum1
16 Dec 1983
TL;DR: In this paper, a three terminal integrated low-resistant series switch circuit (10) which buffers load electronics from extreme input voltage conditions is described, where the series pass transistor is driven toward saturation and is maintained in this state by feedback whereby only that load current required by the load electronics is supplied for increased efficiency.
Abstract: A three terminal integrated low-resistant series switch circuit (10) which buffers load electronics from extreme input voltage conditions. The circuit comprises a series pass transistor (20) the conductivity of which is controlled by control circuitry (22, 24, 28, 32) in cooperation with feedback control (36). In response to the input exceeding a predetermined operating potential the series pass transistor is driven toward saturation and is maintained in this state by feedback whereby only that load current required by the load electronics is supplied for increased efficiency. The control circuitry is responsive to the signal at the input thereof exceeding a predetermined level for rendering the series pass transistor nonconducting to protect the load electronics from extreme voltage excursions. A feature of the circuit is that the epitaxial layer within which the control circuit is formed is operated at a lower voltage than that of the substrate.

Patent
30 Mar 1983
TL;DR: In this article, the network connections of the channels of complementary symmetry MOS FETs in a logic gate or array are altered electrically to program different logic responses to logic inputs.
Abstract: The network connections of the channels of complementary symmetry MOS FET's in a logic gate or array are altered electrically to program different logic responses to logic inputs. To this end, certain of the FET's are gate-injection or substrate-injection MOS FET's.

Patent
29 Dec 1983
TL;DR: In this article, a high voltage circuit with a regenerative circuit coupled to an inverting push-pull buffer and a 5 volt power supply terminal was proposed. But the signal output was not maintained at ground potential when the logic signal was in a second state.
Abstract: A high voltage circuit provides a high voltage signal output in response to receiving a logic signal. The high voltage circuit includes a regenerative circuit which is coupled to a high voltage terminal and a 5 volt power supply terminal. An inverting push-pull buffer responsive to the logic signal provides a signal which is regenerated to the high voltage by the regenerative circuit when the logic signal is in a first state and maintains the signal at ground potential when the logic signal is in a second logic state.

Journal ArticleDOI
C.A. Palesko1, L.A. Akers
TL;DR: This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic and presents results using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.
Abstract: This paper describes a procedure for partitioning logic to minimize the number of gate arrays required to implement the logic. The procedure consists of three algorithms to perform initial, iterative, and interactive logic partitioning. Results are presented using three different logic circuits ranging in size from 14 000 gates to 26 000 gates.

Patent
29 Jul 1983
TL;DR: In this paper, a MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V DD and a logic signal output terminal, each series circuit being comprised of serially connected two N-channel MOS FETs.
Abstract: A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.

Proceedings ArticleDOI
27 Jun 1983
TL;DR: An algorithm for pass transistor simulation using the Yorktown Simulation Engine (YSE) is outlined, and modeling of circuits under this environment is defined, including the analysis of the algorithm's performance for some general circuit types.
Abstract: An algorithm for pass transistor simulation using the Yorktown Simulation Engine (YSE) is outlined. Implementing this algorithm yields an efficient tool for custom VLSI circuit design verification and fault simulation. Modeling of circuits under this environment is defined, including the analysis of the algorithm's performance for some general circuit types. A number of specific examples are discussed in detail.

Journal ArticleDOI
TL;DR: The gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology provided adaptability to evolving logic design with short turnaround time, high packing density competitive with hand layout, compatibility with computer-aided layout and verification tools, and technology updatability.
Abstract: BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells.

Patent
Herchel A. Vaughn1
22 Jun 1983
TL;DR: In this paper, a static CMOS delayed flip-flop uses only a weak P channel transistor for reinforcing a logic high at a control node while using a pair of series connected N channel transistors for reinforcing the logic low at the control node.
Abstract: A static CMOS delayed flip-flop uses only a weak P channel transistor for reinforcing a logic high at a control node while using a pair of series connected N channel transistors for reinforcing a logic low at the control node. Only a single P channel device is required because it can be made to have sufficiently low gain at a relatively small device size so that the control node can have it logic state switched by an N channel device of comparable size.

Journal ArticleDOI
TL;DR: In this paper, the response of GaAs FET logic gates to picosecond light pulses is analyzed and the optimum conditions for optically induced logic level switching are deduced.
Abstract: We report detailed characteristics of the response of GaAs FET logic gates to picosecond light pulses, from which optimum conditions for optically induced logic level switching are deduced. These characteristics include plots of photoinduced output electrical signals versus input dc voltages for the illumination of individual FET's in NOR gates and Inverters. Optically induced logic level switching has applications in high-speed data processing in gigahertz-rate communications links, contactless diagnosis of logic circuits, and picosecond resolution measurements of on-chip response times of logic gates.

Patent
Yigal Brandman1
28 Nov 1983
TL;DR: A programmable logic gate includes first and second complementary field effect transistors having gate terminals connected to receive a first input signal as mentioned in this paper, and the variable resistances can be fusible links or variable resistance semiconductor devices.
Abstract: A programmable logic gate includes first and second complementary field effect transistors having gate terminals connected to receive a first input signal. A first variable resistance is connected in series with the first transistor, and a second variable resistance is connected in parallel with the second transistor. The variable resistances can be fusible links or variable resistance semiconductor devices. By increasing the resistance of the first variable resistance and decreasing the resistance of the second variable resistance, the input signal becomes ineffective in the logic gate. Conversely, by decreasing the resistance of the first variable resistance and increasing the resistance of the second variable resistance, the input signal becomes effective in operation of the logic circuit. In programming the transistors, one transistor is effectively disconnected from the gate and the complementary transistor is effectively shorted.

Patent
16 May 1983
TL;DR: A ternary logic circuit (20) as mentioned in this paper comprises a load element (22) connected to one voltage level and to a node (32), and a logic section (24, 26), connected to a second voltage level, and the same node from which the circuit output is derived.
Abstract: A ternary logic circuit (20) comprises a load element (22) connected to one voltage level and to a node (32) and a logic section (24, 26) connected to a second voltage level and the same node (32) from which the circuit ouput is derived. The two voltage levels including the voltage supply and ground voltage enable the circuit to provide an output at three logic levels "0", "1", and "2", depending on inputs to the logic section. The circuit may be implemented with CMOS technology using, in addition, N-channel or P-channel depletion devices, in different logic formats such as ternary extensions of NAND or NOR gate circuits with the logic section elements arranged in different configurations and combinations of pairs of CMOS devices.

Patent
William J. Ooms1
25 Apr 1983
TL;DR: In this paper, a load-emitter coupled logic circuit is described that utilizes forward biased diodes in the load circuits, and the load circuit may be comprised of a single diode or two or more diode connected in series.
Abstract: Diode load emitter coupled logic circuits is described that utilizes forward biased diodes in the load circuits. The load circuits may be comprised of a single diode or two or more diodes connected in series. If a single diode is used in the load circuits, the slope factor of the diode must be greater than or equal to the slope factor of switching transistors in the logic circuit. External bias circuitry provides a bias current which can be varied for varying the frequency of operation of the logic circuit. High speeds at low power dissipations can be obtained since the switching transistors in the logic circuits do not switch completely on and off.