Showing papers on "Pass transistor logic published in 1984"

Cascode voltage switch logic: A differential CMOS logic family

Abstract: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

A Switch-Level Model and Simulator for MOS Digital Systems

Abstract: The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open," "closed," or "indeterminate." Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; buses; charge sharing; and sneak paths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and operates at speeds approaching those of conventional logic gate simulators. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.

Low power dissipation MOS ternary logic family

Abstract: An MOS ternary-logic family comprising a set of inverters, NOR gates, and NAND gates is proposed. These gates are used to design basic ternary arithmetic and memory circuits. The circuits thus obtained are then used to synthesize complex ternary arithmetic circuits and shift registers. The ternary circuits developed are shown to have some significant advantages relative to other known ternary circuits; these include low power dissipation and reduced propagation delay and component count. For a given dynamic range, the complexity of the new ternary circuits is shown to be comparable to that of corresponding binary circuits. Nevertheless, the associated reduction in the wordlength in the case of the ternary circuits tends to alleviate to a large extent the pin limitation problem associated with VLSI implementation. The authors conclude with an implementation of the cyclic convolution, an application in which a significant advantage can be gained through the use of ternary digital hardware.

Switch-Level Delay Models for Digital MOS VLSI

Abstract: This paper presents fast, simple, and relatively accurate delay models for large digital MOS circuits. Delay modeling is organized around chains of switches and nodes called stages, instead of logic gates. The use of stages permits both logic gates and pass transistor arrays to be handled in a uniform fashion. Three delay models are presented, ranging from an RC model that typically errs by 25% to a slope-based model whose delay estimates are typically within 10% of SPICE's estimates. The slope model is parameterized in terms of the ratio between the slopes of a stage's input and output waveforms. All the models have been implemented in the Crystal timing analyzer. They are evaluated by comparing their delay estimates to SPICE, using a dozen critical paths from two VLSI designs.

Optical parallel logic gates using a shadow-casting system for optical digital computing

Abstract: A new, simple method of optically implementing optical parallel logic gates has been described. Optical parallel logic gates can be implemented by using a lensless shadow-casting system with a light-emitting diode (LED) array as a light source. Pattern logic, i.e., parallel logic for two binary patterns (variables), is simply obtained with these gates; this logic describes a complete set of logical operations on a large array of binary variables in parallel. Coding methods for input images are considered. Applications of the method for a parallel shift operation and optical digital image processing, processing of gray-level images, and parallel operations of addition and subtraction for two binary variables are presented. Comparison of the operation of the proposed optical logic gate with that of array logic in digital electronics leads to a design concept for an optical parallel array logic system available for optical parallel digital computing.

Communication interface connecting binary logic unit through a trinary logic transmission channel

Abstract: A communications interface for transferring data from a first binary logic circuit to a second binary logic circuit by using a trinary logic transmission channel. The first set of binary logic signals is converted into a first set of binary control signals which, in turn, control trinary drivers connected to the transmission channel. The trinary drivers drive the transmission channel to one of three discrete voltage levels as opposed to one of two levels in binary systems. Trinary receivers are located on the second binary logic circuit and are connected to the trinary transmission channel. The receivers produce a second set of binary control signals which are translated into a second set of binary logic signals for use by the second binary logic circuit.

A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection

Abstract: A procedure to derive gate level equivalent circuits for CMOS combinational logic circuits is given. The procedure leads to a model containing AND, OR and NOT gates. Specifically it does not require memory elements as does an earlier model and also uses fewer gates. It is shown that tests for classical stuck-at-0 and stuck-at-1 faults in the equivalent circuit can be used to detect line stuck-at, stuck-open and stuck-on faults in the modeled CMOS circuit.

An algorithm for CMOS timing and area optimization

Abstract: Delay-time optimization for integrated circuits is discussed. A design truly optimized for delay time is seldom practical because the silicon area increases very rapidly when the minimum delay time is approached. The author presents an algorithm which facilitates an intelligent compromise between the delay time and the silicon area of a logic chain. A computer software based on this algorithm can interactively assist the designer in the selection of logic pattern, the number of stages, and the sizes of the transistors. Some basic assumptions are made in this algorithm in order to keep the mathematics manageable. Consequently, some random parameters related to layout and interconnection are not addressed. The intended use of this algorithm is to guide the designer to arrive at an approximately optimized design during the logic definition stage and before the layout stage. Later, when the layout is completed, a circuit simulator should be used to fine-tune the design by incorporating these random layout parameters.

Sequential optical logic implementation

Abstract: An optical system that performs sequential binary logic operations is described. The system consists of a spatial light modulator (SLM) used to provide a nonlinear threshold response and a computer-generated hologram to provide interconnections between logic gates. A 2-D array of logic gates with binary inputs and outputs is formed on the active surface of the SLM. These gates are interconnected by a 2-D array of subholograms, one for each gate. Arbitrary logic circuits consisting of NOR gates and inverters can be implemented, and the system can be reconfigured by changing a single holographic element. The system is demonstrated using a twisted-nematic liquid crystal light valve as the SLM. A test circuit is implemented that includes a synchronous master–slave flip-flop and an oscillator consisting of five inverters in a feedback loop. Experimental results of this test circuit are presented.

Integrated circuit device accepting inputs and providing outputs at the levels of different logic families.

Abstract: An integrated circuit device (10 in Fig. 2; 105 in Fig. 5) containing internal logic and/or memory circuitry (19; 114, 115) is provided with means to receive multiple inputs at the voltage levels of different logic families (Pi-Pi) and with means to provide multiple outputs at the voltage levels of different logic families (Pj-Pn). On-chip input translators (15, 17; 106, 108, 110, 112) receive the inputs at the level of a given logic family and translate to the level required by the internal logic and/or memory circuitry. After performance of logic and/or memory functions, on-chip output translators (16, 18; 107, 109, 111, 113) translate the otput of the internal logic and/or memory circuitry and provide external outputs at the voltage levels of different logic families. The internal logic and/or memory circuitry may be of a single logic family or may be composed of several logic families. On-chip translators may also be added between internal logic and/or memory circuitry of different families (116, 117).

Dynamic logic CMOS circuits

Abstract: A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.

Dynamic Fault Imaging of VLSI Random Logic Devices

Abstract: A technique is described for acquiring and imaging faults in random logic devices such as microprocessors and other VLSI chips. Logic states for both faulty and fault-free devices are imaged separately by means of stroboscopic voltage contrast in a scanning electron microscope and are then stored as incremental time sequences of images. These sequences represent the time evolution of states during a particular device test and are then compared in an image array processor. The divergences or changes between the faulty and fault-free device evolutions represent faults, which are then displayed on a color monitor. The architecture and implementation of the Dynamic Fault Imager is described. Several examples using highly-integrated microprocessors are given, including the imaging of functional failures, voltage marginalities, and critical speed path mapping. A partial classification of faults is presented, as well as a discussion of future trends. The technique appears to have wide application to solving problems in the design and manufacturing of future VLSI devices.

Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals

Abstract: A semiconductor integrated circuit is provided which combines an MOS internal logic circuit (C-MOS in the preferred embodiment) with input and output buffers which have pin-compatibility with ECL circuitry. An ECL-CMOS level-conversion input buffer circuit arranged for a C-MOS internal logic circuit has a pair of emitter-coupled transistors which are responsive to an input signal at an ECL level. Thus, the input buffer circuit operates at a high speed. A CMOS-ECL level-conversion output buffer circuit arranged for the C-MOS internal logic circuit has an amplifying transistor, which has its base responsive to the output signal of the C-MOS internal logic circuit, and an emitter-follower transistor which has its base responsive to the collector signal of said amplifying transistor for generating an output signal at an ECL level at its emitter. Thus, the output buffer circuit operates at a high speed. Utilizing such an arrangement, the circuit can obtain the benefits of lower power consumption for the C-MOS internal logic circuit together with high speed in the buffer stages and ECL compatibility.

D-Latch circuit using CMOS transistors

Abstract: A latch circuit includes a CMOS inverter to which a logic signal is applied to the input through an input terminal, which inverter continues to supply an output signal to its output terminal; and first depletion type p and n-channel MOS transistors connected in series to each other, with the CMOS inverter being interposed therebetween. The latch circuit further includes second depletion type n and p-channel MOS transistors which are supplied, at their gates, with an output signal from the CMOS inverter; the second n-channel MOS transistor being connected between the first p-channel MOS transistor and a power supply terminal, and the second p-channel MOS transistor being connected between the first n-channel MOS transistor and a ground.

Single Event Upset Rate Predictions for Complex Logic Systems

Abstract: Data from spaceborne integrated circuits and ground-based ion bombardment experiments establish that logic devices ranging from memories to microprocessors are susceptible to single event-induced errors (1). The circuit level upset mechanism for static and dynamic RAMs is understood (2), and recently comparable mechanisms responsible for the single event vulnerability of random logic networks within these devices have been identified (3). Additionally, a technologyindependent correspondence between experimental measurements of single event upset cross section and LET threshold and the single event error rate measured in digital logic arrays in a standard cosmic ion environment has been formulated (4). While many questions concerning the basic mechanisms involved in single event errors remain, these advances have provided essential components for an empirical assessment of single event effects in spaceborne systems.

Integrated logic circuit incorporating a module which generates a control signal that cancels switching noise

Abstract: A circuit having reduced susceptibility to noise includes a plurality of drivers coupled to a current bus; each driver receives a logic signal on a control terminal and operates to pass a large current when the logic signal is a one and pass a small current when the logic signal is a zero; the current bus has a parasitic inductance which generates a noise signal when the logic signals switch; noise on the current bus is parasitically coupled to the control terminal of each driver; and a plurality of noise reducing modules respectively couple to the control terminal of each driver and a common bus Each module that receives a switching logic signal generates a control signal on the common bus that is similar in shape and opposite in polarity to the noise signal; and each module that does not receive a switching logic signal couples the control signal from the common bus to the control terminal to which it is connected

Delay analysis of Si NMOS Gbit/s logic circuits

Abstract: A simple piecewise-linear analysis method which can be used to predict the logic propagation delay (/spl tau//SUB d/) for fine-line Si NMOS logic gates is presented. The set of equations derived shows explicitly the dependence of /spl tau//SUB d/ on inverter noise margins, driver transconductance, load current, node capacitance, driver and load input conductances, and driving waveshapes. Submicron-channel Si NMOS has demonstrated a /spl tau//SUB d/ as low as 30 ps for unity fan-in and fan-out ring oscillators. It is shown that the p-n junction capacitances of the driver and load devices account for up to 50% of the total logic gate capacitances. If reduced (as in SOI for example), Si NMOS logic gates might produce a /spl tau//SUB d/ as low as 15-20 ps. The delay analysis can be used to predict the operation of larger circuits. An example using a flip-flop frequency divider is given.

CMOS Logic circuit

Abstract: A CMOS logic circuit has MOSFETs of a first conductivity type in which each terminal is connected to a corresponding input terminal of the CMOS logic circuit, delay elements are inserted between the input terminals of the CMOS logic circuit and the gates of the MOSFETs of the first conductivity type, an output inverter is inserted between the remaining terminals of each of the MOSFETs of the first conductivity type and the output terminal of the CMOS logic circuit, and in which a MOSFET of a second conductivity type is inserted between the input terminal of the output inverter and a power source which is controlled by the output from the output inverter.

Non-overlapping clock CMOS circuit with two threshold voltages

Abstract: A set of clock-controlled CMOS logic circuits employ a single pair of non-overlapping clocks controlling a set of transmission gates that have only a single pass transistor and a compensating non-standard threshold voltage in a portion of the logic gates.

Timing, Logic and Mixed-Mode Simulation for Large MOS Integrated Circuits

Abstract: Many different forms of simulation can be used for the analysis of large digital integrated circuit designs at the various stages of the design process. They may be classified as Behavioral (also called algorithmic or functional) simulators, Register Transfer Level (RTL) simulators, Gate Level Logic simulators, timing simulators, and circuit simulators, as illustrated in Fig.1.1.

Current compensation for logic gates

Abstract: Current compensation for inverting logic gates is achieved by using a current mirror having a controlling leg equivalent to the input structure of the logic gate which is in the controlled leg. The controlling leg receives a reference voltage signal equal to the input signal to the logic gate which creates a leakage current. A plurality of controlled legs can be used with a single controlling leg to provide current compensation for a plurality of logic gates.

CMOS Cell array with transistor isolation

Abstract: A new technique for forming CMOS custom logic circuits is disclosed wherein standard cells (10,12,14) are used and the prior art technique of field oxide isolation (16) is replaced with transistor isolation (68-71). That is, the boundaries (18,20,22,24) between the cells are formed by transistors that are permanently "off", i.e., tied to the positive or negative voltage supply, depending on whether the transistors are p-channel or n-channel devices, respectively. Therefore, instead of having to deposit separate p+ and n+ source/drain diffusions for each cell, as in the prior art, a single p+ diffusion strip (60) and a single n+ diffusion strip (62) are utilized, where the polysilicon mask of both the logic and isolation transistors defines the cell sizes. Thus, the p+ and n+ diffusions become generic steps which do not vary from circuit to circuit, decreasing the turnaround time associated with custom logic circuit layout and design.

Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs

Abstract: The series connection between operating voltage terminals of the channels of field effect transistors with electrically alterable threshold voltage, programmed one for conduction and the other for non-conduction in response to programming voltage on their gate-to-gate connection, forms a programmable latch. A pair of such latches, or such a latch and a complementary-pair logic inverter, form a programmable complemented latch. The programmable complemented latch can be used to selectively enable a complementary-pair transmission gate, or to selectively enable a complementary-pair logic inverter, or to alternatively enable a transmission gate and a logic inverter. This last operation can be carried out, for example, in a modified Annis exclusive-OR gate configuration, for selectively inverting or not inverting a logic input.

Frequency encoded logic devices

Abstract: Logic devices for frequency encoded trinary logic signals are simulated by standard binary circuits. The binary circuits include frequency sensing and frequency selecting devices at the inputs and outputs thereof for decoding the frequency encoded trinary logic signals to binary level logic signals and for frequency encoding the resulting binary output to trinary logic signals. Optical encoding using the three primary light frequencies provides a convenient trinary signal format for the frequency encoded signals. A latch register, a shift register, a half adder and full series and parallel adder circuits are disclosed.

Method of arranging logic circuit devices on logic circuit board

Abstract: In the fabrication of an electronic circuit such as an integrated circuit, a method of determining the arrangement of logic circuit devices on a circuit board on the basis of a logic data defining the logic circuit devices and the interconnections among them. The logic circuit devices are classified in groups in accordance with a degree that each signal line connected with the logic circuit devices requires the expedition of signal propagation therethrough. First, the logic circuit devices belonging to the group pertinent to the highest degree are arranged, and next those belonging to the group pertinent to the second highest degree are arranged. Such a processing is carried out for all the groups.

Protection apparatus for a transistor inverter

Abstract: A protection apparatus for a transistor inverter including a detecting circuit connected to a logic circuit detecting the base current and the collector-emitter voltage of a pair of transistors in the inverter to be protected. A logic circuit performs a logical operation on a binary signal based on the base current of one of the transistors and the collector-emitter voltage of the other of the transistors in the pair. When a short circuit in either one of the transistors is detected, the logic circuit operates a protective thyristor which causes a short circuit current to flow through fuses connected to the transistors, thereby electrically cutting off the transistors by the blow out of the fuses.

Integrated circuit having three power bases and proportioned parasitic resistive and capacitive coupling to reduce output noise

Abstract: A circuit integrated into a substrate and having improved noise immunity comprises logic gates for receiving and switching current from a first bus to produce a logic signal; a resistor for receiving and passing a small bias current from a second bus indicating the state of the logic signal; a transistor for receiving and passing a large drive current from a third bus in response to bias current; and the first bus has a relatively large parasitic coupling serially through the logic gates, substrate, and resistors to the second bus; while the first bus has a relatively small parasitic coupling serially through the logic gates, substrate, and transistor to the third bus.

Pulsed multichannel protection system with saturable core magnetic logic units

Abstract: The dynamic logic of each channel of a multi-channel protection system for a nuclear power plant provides a trip logic path and a global bypass logic path by which pulse signals from a clock source may be transmitted to a dc-to-dc power converter which energizes the undervoltage coils for a pair of contactors in the reactor trip switchgear. Each of the logic paths is constructed of basic logic units which in turn, each include a toroidal core of rectangular, hysteresis loop magnetic material having a control winding which must be energized by a dc current in order for pulses applied to an input winding to appear at an output winding. Blockage of pulses through any one of the serially connected basic logic units in a logic path terminates the flow of pulses to the converter through that logic path. The control windings of corresponding logic units of the trip logic path in each channel are energized by one of a set of redundant sensors which monitor one of a plurality of reactor trip parameters. Dynamic voting logic appropriate for existing conditions is implemented in part by microprocessors in each channel which gather status information from the other channels through isolated, fiber optic, multiplexed data links and provide the switching logic for alternate paths for energization of the individual basic logic unit control windings, so that for instance, coincidence of trip signals from corresponding sensors in at least two out of four unbypassed channels is required to trip the reactor switch gear. Local bypasses provide additional energization paths for the control windings of basic logic units associated with sensors which are out of service or being repaired. Pulses propagate through the basic logic units of the global bypass path when an entire channel is taken out of service for testing or maintenance. Interlocks between logic units in the trip logic and global bypass logic paths permit only one path to deliver pulses to the converter at any given instant.

Optical threshold logic elements for digital computation.

Abstract: A hybrid integrated optical threshold logic element is proposed for fast digital computation on a chip level. Each input and output optical beam occupies a separate channel and is coupled directly to the source. This suggests the possibility of achieving reliable optical digital operation in a complex network. Such a network is expected to be particularly compact because one or several threshold logic elements may replace many simple optical logic elements. The devices are also capable of high-speed programmability, so the same set of elements can serve different functions. Applications to conventional arithmetic computation and to high-speed residue arithmetic computation are presented.