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Showing papers on "Pass transistor logic published in 1987"


Journal ArticleDOI
TL;DR: A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques.
Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.

177 citations


Journal ArticleDOI
TL;DR: In this article, a new family of dc-powered Josephson junction digital devices, the Rapid Single Flux Quantum (RSFQ) logic, is described, which use overdamped Josephson junctions and two-junction interferometers to store, pass and process the digital information presented in form of single flux quanta.
Abstract: A new family of dc-powered Josephson junction digital devices, the Rapid Single Flux Quantum (RSFQ) logic, is described. The devices use overdamped Josephson junctions and two-junction interferometers to store, pass and process the digital information presented in form of single flux quanta. We have carried out extensive numerical simulation of the dynamics of the RSFQ logic gates and of some more complex circuits including serial full adder and reversible shift register, within the standard microscopic-theory ("Werthamer") description of Josephson junctions. The minimum clock cycles of the basic RSFQ circuits turn out to be as small as 2.5 ps. The most promising ways to use the RSFQ logic circuits at the present stage of development of the Josephson junction digital technology are discussed.

137 citations


Patent
John E. Mahoney1
07 Oct 1987
TL;DR: In this paper, the integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation.
Abstract: The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.

132 citations


Journal ArticleDOI
TL;DR: The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults.
Abstract: Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.

82 citations


Patent
30 Nov 1987
TL;DR: In this article, a DRAM cell with a storage node (18), a pass transistor (76), and a polysilicon word line (84) is formed within an oxide isolated trench (68), thereby providing high soft error immunity.
Abstract: A DRAM cell (8) having a storage node (18), a pass transistor (76) and a polysilicon word line (84) formed within an oxide isolated trench (68), thereby providing high soft error immunity. A write bit line (66) functions as the drain region (78) of the pass transistor (76) and is isolated from the substrate by a oxide isolation (64), thereby enhancing soft error immunity. The trench (68) includes an annular opening for providing intimate contact between the past transistor conduction channel (82) and the single crystal silicon substrate (36). During processing, the polysilicon conduction channel (82) of the pass transistor (76) is converted into single crystal silicon, thereby providing enhanced performance of the cell (8).

57 citations


Journal ArticleDOI
TL;DR: This work presents a global approach to timing performance optimization, which involves operations at the logic, topological, and physical level of abstraction of the circuit, and applies it to a 32-bit microprocessor design.
Abstract: The quality of the design of large-scale integrated circuits is determined by such figures of merit as silicon area, power consumption, and switching-time performance. We address here the problem of the automatic synthesis of digital circuits with the goal of achieving high-performance designs. We assume we are given an intermediate circuit representation that optimizes area and/or power. We use timing optimization techniques to improve the circuit performance, possibly at the expense of the other figures of merit. We consider general classes of digital circuits, with a given partition into registers, combinational blocks, and I/O ports. Circuit performance is related to the worst-case propagation delay of signals between two register boundaries. In this context, circuit performance optimization is equivalent to minimizing the critical path delay through the combinational circuits. We assume a multiple-level implementation of the combinational logic, by means of an interconnection of logic gates implementing arbitrary multiple-input, single-output logic functions. We consider dynamic CMOS implementation of the logic gates, operating in the domino mode. We present a global approach to timing performance optimization, which involves operations at the logic, topological, and physical level of abstraction of the circuit. In particular, at the logic level, we look for optimal structures of multiple-level combinational networks. At the topological level, we search for the optimal positions of gates or groups of gates. At the physical design level, we optimize MOS device sizes. The algorithms are described, together with their implementation and the interface to the Yorktown Silicon Compiler system, which is an automated synthesis system described in [7]. The results of applying timing-performance optimization to a 32-bit microprocessor design are reported.

49 citations


Journal ArticleDOI
TL;DR: This logic technique offers greater area efficiency, higher speeds of operation, and simpler design algorithms than conventional CMOS pass-transistor logic.
Abstract: This logic technique offers greater area efficiency, higher speeds of operation, and simpler design algorithms than conventional CMOS pass-transistor logic. Experimental results and the automated techniques used in implementing efficient pass-transistor layouts are presented. The application of CMOS differential pass-transistor logic design in custom applications is also discussed.

47 citations


Patent
Mark T. Smith1
04 May 1987
TL;DR: In this article, a hardware switch level simulator for LSI/VLSI MOS circuits capable of simulating circuits with pass transistors and performing timing analysis is presented, where the simulator has a stack memory containing lists of nodes to be operated on, a solve unit having programmed logic arrays for performing simulation steps using Bryant algebra plus an addition step for detecting unblocked paths to a controlling gate of a pass transistor, a traversal unit having gate memory storing a gate list of nodes for each transistor and having link memory stored a netlist of transistor switches with parameters such as
Abstract: A hardware switch level simulator for LSI/VLSI MOS circuits capable of simulating circuits with pass transistors and performing timing analysis. The simulator has a stack memory containing lists of nodes to be operated on, a solve unit having programmed logic arrays for performing simulation steps using Bryant algebra plus an addition step for detecting unblocked paths to a controlling gate of a pass transistor, a traversal unit having gate memory storing a gate list of nodes for each transistor and having link memory storing a netlist of transistor switches with parameters such as preset transistor switch state, transistor strength, and pointers to nodes to which a transistor connects. A timing unit performs delay calculations. In order to simulate pass transistor circuits, the traversal unit has two sets of memory addressing gates. One set ordinarily accesses link memory, while a second set ordinarily addresses gate memory. During source to gate path detection, the second set can be multiplexed to also address link memory.

44 citations


Patent
Stephen Sunter1
29 Oct 1987
TL;DR: In this paper, the bias current circuit is formed by a transistor and a resistance element which are serially connected across the power supply of the logic circuit, and the current passing through each bias transistor depends upon the relative dimensions between that transistor and the respective bias circuit transistor.
Abstract: Current-mirror circuitry is utilized on a MOS integrated circuit for regulating the amount of current entering the pre-charged nodes of a pre-charged logic circuit. The current-mirror circuitry involves a series of bias transistors, each extending in parallel with a respective one of the pre-charge transistors, and a bias current circuit. The bias current circuit is formed by a transistor and a resistance element which are serially connected across the power supply of the logic circuit. The gate of the bias circuit transistor is connected to the gates of the bias transistors, and the current passing through each bias transistor depends upon the relative dimensions between that transistor and the respective bias circuit transistor. The value of the resistance element determines the amount of current passing through the bias circuit transistor and therefore through the bias transistors.

38 citations


Proceedings ArticleDOI
01 Jan 1987
TL;DR: The process architecture and results of an 0.8µm 5V CMOS logic technology, which is a factor of two faster than current 1.2µM CMOS technology, are reported on.
Abstract: This paper reports on the process architecture and results of an 08µm 5V CMOS logic technology The process, which is a factor of two faster than current 12µm CMOS technology, features seven optically patterned levels with 08µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels

38 citations


Patent
13 Aug 1987
TL;DR: In this article, a pull-up transistor (N1), a first pulldown transistor, a second pull-down transistor and a logic circuit (15) are used to reduce ground bounce noise.
Abstract: An output buffer includes a pull-up transistor (N1), a first pull-down transistor (N3), a second pull-down transistor (N8), and a logic circuit (15). The logic circuit (15) is responsive to a data input signal making a high-to-low transition and the output signal making a high-to-low transition for maintaining the second pull-down transistor (N8) turned-off until after an output node has made the high-to-low transition, thereby reducing significantly the ground bounce noise.

Patent
David J. Hathaway1
02 Dec 1987
TL;DR: In this paper, the gates of a logic network are levelized in a forward and backward direction to determine the worst path length of the network, and then a gate in such a worst path is selected in accordance with a specified scoring function.
Abstract: An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

Patent
04 Aug 1987
TL;DR: In this article, the output voltage of the driver transistors is modulated by output voltage itself, which is the voltage on the gate of the transistor which is providing the particular logic state.
Abstract: An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the ends of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors in controlled by controlling the voltage on the gate of the transistor which is providing the particular logic state. This control reduces di/dt from that typically provided at the very beginning of a logic state transition but increases it over that typically provided immediately thereafter for the purpose of optimizing logic state transition speed for a given maximum di/dt. The control of the gate of the driver transistor is modulated by the output voltage itself.

Patent
04 Aug 1987
TL;DR: In this paper, a dynamic logic circuit with a collector, a base and an emitter is provided, with the collector-emitter current path connected between the output of the circuit and a first potential, and a precharging device is coupled between a second potential and the output to precharge the output according to at least one clock signal.
Abstract: A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.

Patent
25 Feb 1987
TL;DR: In this paper, the authors proposed a technique to reduce the voltage across one or more transistors in various complementary (e.g., CMOS) logic circuits while still obtaining a full logic swing at the output of the logic.
Abstract: As integrated field effect devices are scaled to smaller dimensions, the electric field in the channel increases for a constant operating voltage. This induces "hot electron" effects that reduce device reliability. The present invention reduces the voltage (and hence electric field) across one or more transistors in various complementary (e.g. CMOS) logic circuits. This is achieved while still obtaining a full logic swing (e.g., 0-5 volts) at the output of the logic. The technique also allows the retention of previous voltage levels (e.g., 5 volts) for operation of other portions of the integrated circuit (e.g., dynamic memory cells).

Patent
04 Dec 1987
TL;DR: In this article, a logic circuit simulation method for simulating a logic circuits including a plurality of logic blocks is presented, in which after having simulated the whole simulation object logic circuit, signal variation information of an arbitrary logic block is taken out from the simulation result, the information thus taken out is given to the logic blocks, and a renewed simulation is executed for every logic block.
Abstract: A logic circuit simulation method for simulating a logic circuit including a plurality of logic blocks, in which after having simulated the whole simulation object logic circuit, signal variation information of an arbitrary logic block is taken out from the simulation result, the information thus taken out is given to the logic blocks, and a renewed simulation is executed for every logic block.

Patent
Fujio Masuoka1, Kiyofumi Ochii1
11 Sep 1987
TL;DR: In this paper, a logic circuit consisting of at least one signal input terminal, an output terminal, and an output circuit including a first bipolar transistor coupled between the output terminal and a reference potential terminal, is described.
Abstract: A logic circuit comprises at least one signal input terminal, an output terminal, an output circuit including a first bipolar transistor coupled between the output terminal and a reference potential terminal, to discharge the output terminal, and an MOS type logic circuit for supplying to the base of the first bipolar transistor a signal of a level corresponding to an input signal supplied to the at least one signal input terminal. The logic circuit further comprises a control MOS transistor coupled between a power source terminal and the base of the bipolar transistor, for supplying part of the base current to the bipolar transistor in response to a signal at the output terminal.

Patent
26 May 1987
TL;DR: In this paper, a logic level translator circuit includes capacitive coupling to facilitate rereferencing and differentiating of input logic signals and a feedback circuit which holds one of the devices in a conductive state and the other in a nonconductive state to provide an output signal having predetermined logic levels.
Abstract: A logic level translator circuit includes capacitive coupling to facilitate rereferencing and differentiating of input logic signals. An input amplifier having complementary devices is responsive to the differentiated signals to provide control signals to a feedback circuit which holds one of the devices in a conductive state and the other in a non-conductive state to provide an output signal having predetermined logic levels. Threshold voltage generating circuits biases each of the devices.

Patent
30 Nov 1987
TL;DR: In this article, a two transistor gain-type DRAM cell is constructed in a trench to optimize wafer area requirements, where a vertical pass transistor (12) and a gain transistor (24) are used to change the voltage of the read bit line depending upon the charge stored in the capacitor storage node (18).
Abstract: A two transistor gain-type dynamic random access memory (DRAM) cell (8) formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).

Patent
02 Jul 1987
TL;DR: In this article, a fast write CMOS memory cell includes two CMOS inverters connected in a latched configuration with the first inverter having a P-channel transistor (98) and an N-channel transistors (102), and the second inverter had a Pchannel transistor and an n-channel Transformer (N-Transformer).
Abstract: A fast write CMOS memory cell includes two CMOS inverters connected in a latched configuration with the first CMOS inverter having a P-channel transistor (98) and an N-channel transistor (102) and the second inverter having a P-channel transistor (90) and an N-channel transistor (96). The output of the first inverter is connected to the input of the second inverter with the output of the second inverter connected to the input of the first inverter through a pass transistor (104). The pass transistor (104) is conductive during the static mode of operation and is nonconductive during the write operation. During write, the input of the first inverter is forced to a predetermined logic state with the pass transistor (104) nonconductive. After write, the pass transistor (104) conducts and reconfigures the latch.

Journal ArticleDOI
TL;DR: It is shown that a good ordering for processing the blocks in a network is possible only in the absence of any form of feedback among the blocks, and a linear time algorithm is presented that detects the strongly connected blocks, which are then flagged for simulation using special dynamic windowing techniques.
Abstract: This paper describes the algorithms used in a presimulation phase to partition an MOS digital network into various special subnetworks (or blocks) and to order these subnetworks for processing in a switch-level timing simulator such as MOSTIM [1]. A transistor-level SPICE2-type [3] description of the network is assumed to be provided. The key to the partitioning strategy is to divide the set of enhancement transistors into driver and pass transistors. The driver transistors are then grouped together in a de-connected sense to form multiple-input single-output combinatorial logic blocks, while the pass transistors are grouped together to form pass transistor blocks. A graph algorithm performs the partitioning step in computation time that is linear with the number of enhancement transistors. The partitioning step is an automatic process that is completely transparent to the user. The partitioned blocks are then ordered for simulation such that, whenever possible, a block is scheduled for processing only after all its input waveforms are known. A clear and precise notion of feedback among the various blocks in the partitioned network is introduced, and a distinction is made between feedback among different blocks and feedback internal to a block. It is shown that a good ordering for processing the blocks in a network is possible only in the absence of any form of feedback among the blocks. In case of a partitioned network with feedback, a linear time algorithm is presented that detects the strongly connected blocks, which are then flagged for simulation using special dynamic windowing techniques [4]. The strongly connected components are then topologically ordered for simulation.

Patent
Osam Ohba1, Tetsu Tanizawa1
21 May 1987
TL;DR: In this article, a complementary logic circuit which has high switching speed and low power consumption is presented. But the circuit is composed of a first stage comprising a complementary MIS-FET, and an output stage comprising complementary bipolar transistors or complementary vertical FETs, which pull up or pull down the amplitude of the output signal almost equal to the power supply voltages.
Abstract: A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit is composed of a first stage comprising a complementary MIS-FET, and an output stage comprising complementary bipolar transistors or complementary vertical FETs. The output stage is provided with pull-up and pull-down elements, which pull up or pull down the amplitude of the output signal almost equal to that of the power supply voltages. Accordingly, the lack of sufficient amplitude in the conventional Bi-MIS circuit to drive the C-MIS circuit is improved, and it secures the stable operation of C-MIS logic circuits.

Patent
12 Feb 1987
TL;DR: Improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors (24, 26), respectively, separated by clocked inverters (20) as discussed by the authors.
Abstract: Improved logic circuit employing dynamic CMOS logic and having alternating logic employing first and second conductivity type transistors (24, 26), respectively, separated by clocked inverters (20) The circuit employs a single clock signal (CK) to synchronize the dynamic logic operations of said logic gates and, along with a second, complement clock signal (CK), said clocked inverters (20) Precharge transistors (28, 30, 32, 34) of each conductivity type are slowed slightly with respect to logic transistors (24, 26), and the complement clock signal is delayed slightly with respect to the clock signal, thereby providing racefree logic operations An inplementation in a PLA is disclosed employing two logic planes (10, 12) for implementing arbitrary logic equations on input logic signals (14) The first logic plane (10) and second logic plane (12) are evaluated on separate phases of a complement clock signal (CK) and are separated by a clocked latch/inverter (20) for providing correct logic evaluation between the logic planes

Journal ArticleDOI
TL;DR: In this paper, a 4-bit digital counter circuit with three operating modes of counting, data-loading and clearing has been demonstrated using 3μm-Nb/Al-oxide/Nb junction process.
Abstract: A new Josephson 4-bit digital counter circuit has been demonstrated. Direct-coupled data-latch units which consists of a four-junction logic(4JL) gate family are utilized to make a flip-flop circuit for counting. The counter is designed to be driven by a two-phase mono-polar power supply. The counter circuit has been fabricated using 3μm-Nb/Al-oxide/Nb junction process. The counter has three operating modes of counting, data-loading and clearing which can be adapted to Josephson digital logic system. Experimental tests have been carried out successfully for these operating modes. Computer simulations indicate that the 4-bit counter operates in 315ps.

Patent
Hiep V. Tran1
18 Dec 1987
TL;DR: In this paper, a high-speed level shifter was used to convert ECL logic levels to CMOS logic levels for use in an ECL Bi-CMOS circuit, where a CMOS inverter was connected to the output of an emitter coupled pair through a resistor.
Abstract: A high-speed level shifter converts ECL logic levels to CMOS logic levels for use in an ECL BiCMOS circuit. A CMOS inverter (34) is connected to the output of an emitter coupled pair through a resistor (36). A current reference circuit ensures that the voltage drop across the resistor (36) is such to shift the ECL logic level to the trip point of the CMOS buffer.

Patent
27 Apr 1987
TL;DR: In this article, a monodirectional logic form is provided using a bistable circuit of the set-rest type comprised of two cMOS inverters connected in parallel to a source of power (V dd ) by a power-down p-channel MOS transistor.
Abstract: A monodirectional logic form is provided using a bistable circuit of the set-rest type comprised of two cMOS inverters connected in parallel to a source of power (V dd ) by a power-down p-channel MOS transistor. Each of the cMOS inverters is comprised of a first p-channel MOS transistor in source-drain-drain-source series with an n-channel MOS transistor. Two signal-pass n-channel MOS transistors are provided, one a signal-pass transistor connected as a series switch in a first signal (d) line to the input terminal of one cMOS inverter and the output terminal of the other cMOS inverter, and the other a signal-pass transistor connected as a series switch in a second complement signal (d) line to the input terminal of the other cMOS inverter and the output terminal of the one cMOS inverter. The cMOS inverters are thus directly cross-coupled, input to output, and the input to each is gated by one of the pass transistors, while a first phase of a nonoverlapping two-phase clock signal source is applied to the gates of the power-down and signal-pass transistors. A set-reset circuit coupled in series, either directly or by switching functions is connected to receive the second phase clock signal. The signal pass transistors are connected to mutually exclusive switching functions (series-parallel nMOS network) that provide current paths to circuit ground in response to data signals, or circuit paths to the output terminals of another set-reset circuit.

Patent
02 Oct 1987
TL;DR: In this article, an overcurrent protection circuit for an inverter device including three arms each composed of a pair of series connected electric gates, a junction therebetween being connected to a load and opposite ends being connected across a d.c. power source, and adapted to supply a three-phase a.k.a.
Abstract: An overcurrent protection circuit for an inverter device including three arms each composed of a pair of series connected electric gates, a junction therebetween being connected to a load and opposite ends being connected across a d.c. power source, and adapted to supply a three-phase a.c. power to the load by on-off controlling the electric gates sequentially according to on-off signals of the electric gates supplied from a control circuit. Majority logic circuitry is provided, and stress conditions in the electric gates which receive substantially a stress produced when the electric gates are turned off are detected in order to release these gates from a large stress exerted on the gates when an output short-circuit occurs. The majority logic circuitry control the sequence of turning off the electric gates so that the stress on the detected gate is reduced, to protect the gates from damage due to excess stress on the gates when the output short-circuit occurs.

Patent
11 Jun 1987
TL;DR: In this paper, a pull-to-center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.
Abstract: ACTIVE LOAD NETWORK ABSTRACTAn active load network for a device under test includes a logic circuit for anticipating the out-put state of the device under test and for turning on either a current source of a current sink to properly load its output. The current sink and current source each comprise a pair of CMOS transistors connected in series. One of each transistor pair turns on to either source or sink current and the other provides a variable impedance controlled by the voltage at its gate to regulate the amount of current. A pull-to-center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.

Patent
Masataka Matsui1
30 Mar 1987
TL;DR: In this article, a Bi-CMOS logic circuit with a totem pole-type output buffer and a latch circuit has been proposed to control the base current of a pull-down NPN bipolar transistor.
Abstract: A Bi-CMOS logic circuit having a totem pole-type output buffer, a CMOS logic circuit, and a latch circuit. The output buffer comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. The CMOS logic circuit controls the base current of the pull-up NPN bipolar transistor. The latch circuit controls the base current of the pull-down NPN bipolar transistor. The latch circuit includes at least two N-type MOSFETs. The first MOSFET has a gate coupled to the input terminal of the CMOS logic circuit, a drain connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor. The second MOSFET has a drain coupled to the input terminal of the CMOS logic circuit, a gate connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.

Patent
28 Sep 1987
TL;DR: In this article, a test overlay circuit for interposing between logic blocks of a circuit to be tested is arranged to operate as a conventional buffer between the logic blocks in a first mode of operation but is provided with scan-in and scan-out ports, a register and multiplexers providing path controlling.
Abstract: A test overlay circuit, for interposing between logic blocks of a circuit to be tested, is arranged to operate as a conventional buffer between the logic blocks in a first mode of operation but is provided with scan-in and scan-out ports, a register and multiplexers providing path controlling mean enabling test patterns to be loaded into the register from the scan-in port and fed from the register to the downstream logic block, or enabling data-in (a test pattern) from the up-stream logic block to be fed to the register. The circuit enables the simultaneous loading, receiving and sending of discrete test patterns for testing the logic blocks.