Showing papers on "Pass transistor logic published in 1988"

Timing optimization of combinational logic

Abstract: An algorithm for speeding up combinational logic with minimal area increase is presented. A static timing analyzer is used to identify the critical paths. Then a weighted min-cut algorithm is used to determine the subset of nodes to be resynthesized. This subset is selected so that the speedup is achieved with minimal area increase. Resynthesis is done by selectively collapsing the logic along the critical paths and then decomposing the collapsed nodes to minimize the critical delay. This process is iterated until either the timing requirements are satisfied or no further improvement can be made. The algorithm has been implemented and tested on many design examples with promising results. >

Static timing analysis of semiconductor digital circuits

Abstract: The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

Junction degradation in bipolar transistors and the reliability imposed constraints to scaling and design

Abstract: The stress-induced leakage current is predominantly a Shockley-Read-Hall-like generation-recombination current. As the stress progresses, the leakage current increases, eventually reaches a maximum and then decays. The leakage current lowers the current gain at low biases. It affects the narrow-emitter transistors more since it is proportional to the emitter edge length. But, its impact is less significant if the transistor is operated at a high V/sub be/, as required by constant-current scaling. The loss of the current gain does not affect the circuit speed directly. Instead, it reduces the logic swing and thus the noise margin of the circuit. The design to absorb the degradation with a larger initial logic swing results in a speed penalty. The reverse-stress-induced junction degradation can be eliminated by properly designing the circuit There is no concern for emitter-coupled logic (ECL) circuits when the logic swing is less than the V/sub be/ of the transistors. >

Programmable summing functions for programmable logic devices

Abstract: A programmable logic device includes a programmable logic array and an output logic macrocell The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state

On the design of robust testable CMOS combinational logic circuits

Abstract: The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable. >

High-efficiency DC-to-DC power supply with synchronous rectification

Abstract: A synchronous rectifier power supply circuit has a pair of power MOS transistors connected in series with the primary and secondary of a transformer, respectively, and another power MOS transistor connected across an inductive load on the secondary side. The gates of the pair of transistors are driven by a pulse source which is pulse-width modulated in response to the load voltage, and the other transistor has its gate driven by the inverse of the pulse source. To prevent current spikes and power losses due to the pair of transistors being on during a transition period at the same time the other transistor is on, a high-gain bistable logic circuit is used to drive the gates; A NOR gate prevent the gate of the other transistor from rising to a turn-on voltage until the gates of the pair of transistors are at below a turn-on voltage. A second NOR gate prevents the gates of the pair of transistors from reaching a turn-on voltage until the gate of the other transistor is below a turn-on voltage.

On path selection in combinational logic circuits

Abstract: The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches. >

An architecture for electrically configurable gate arrays

Abstract: A novel architecture for CMOS electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead need to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated. >

Fast CMOS ECL receivers with 100-mV worst-case sensitivity

Abstract: CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process. >

Implementation of iterative networks with CMOS differential logic

Abstract: An improved differential CMOS logic family called enabled/disabled CMOS differential logic (ECDL) is presented. An extension to this logic technique which enables the implementation of iterative network arrays is also presented. Two simple logic functions, a Gray-to-binary decoder and an XOR cell, are implemented to demonstrate this methodology. >

CMOS inverter having temperature and supply voltage variation compensation

Abstract: A semiconductor integrated circuit comprises a pair of P-channel and N-channel MOS output transistors connected in series between a power source voltage node and a ground node, a first logic circuit for controlling a gate potential of the P-channel MOS output transistor, a first current control circuit for controlling a current flowing into a ground potential path of the first logic circuit, a second logic circuit for controlling a gate potential of the N-channel MOS output transistor, a second current control circuit for controlling a current flowing into a power source potential path of the second logic circuit, and the first and second current control circuits having a current-temperature characteristic and a current-power source voltage characteristic which are inversely proportional to those of the MOS output transistors. With such an arrangement, the power source voltage dependency and the temperature dependency of the MOS output transistors are cancelled out by the control currents of the first and second current control circuits. Thus, the output voltage of the output circuit depends little on the change of the power source voltage and the operating temperature.

LOGEX—an automatic logic extractor form transistor to gate level for CMOS technology

Abstract: A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations. >

Fault detection of combinational circuits based on supply current

Abstract: A fault detection technique is proposed which can detect logical faults in combinational circuits by measuring the supply current instead of the output logic, and the effectiveness is evaluated by experiments of the circuits made of TTL (transistors-transistor logic) ICs. This technique is based on the assumption that the supply current will be changed by faults in the logic circuits. A generation mechanism of current variation is represented by an autoregressive model, and faults are detected by using pattern-recognition methods. >

Multiple-valued logic and optimization of programmable logic arrays

Abstract: Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression. >

Method for designing pass transistor asynchronous sequential circuits

Abstract: A method for designing and constructing pass transistor asynchronous sequential circuits, and a class of pass transis tor asynchronous sequential circuits designed in accordance with the inventive method. The inventive circuit design method generates a design for each next state variable, Yi, of an asynchronous pass transistor circuit, where each design corresponds to a portion of the circuit. In a first preferred embodiment, the invention produces an asynchronous circuit design comprising a pass transistor network and a buffer (having no long term memory) for receiving the output of the pass transistor network. In a second preferred embodiment, the inventive method results in a critical race free, asynchronous circuit design comprising an enable pass transistor network, a disable pass transistor network, and a buffer (including a memory) for receiving the output of both pass transistor networks. In either embodiment, the invention results in circuits comprising pass transistor networks that are identical in structure for each next state variable Yi (although different sets of constant input signals are applied to each network). It is within the scope of the invention to design and construct circuits having this architecture in accordance with a structured layout including an input section, a logic section implementing the next state functions, a buffer section, and a feedback section. The logic section preferably includes a pass transistor matrix programmed with either a diffusion-contact-metal transistor structure or a metal jumper structure. The feedback lines preferably are metal lines that are programmed by making contact with the gate lines feeding the pass transistors.

Soft error resistant data storage cells

Abstract: A CMOS data cell having increased immunity to single event upsets is disclosed. The cell includes a first CMOS inverter and a second CMOS inverter which have their respective storage nodes interconnected by cross-coupling connections. The respective storage nodes of the cell are connected through word line or write clock transfer gates to bit lines or data bus lines which serve to both write in and read out the data state of the cell. The soft error resistant data cell further includes six transistors which provide the hardening features to the data storage cell design. Two data state control transistors (one for each storage node) have their drain electrodes connected to a data storage node and their source electrodes connected to the power supply rail. Each of the data state control transistors is gated by the word line voltage via a transfer device or pass transistor that is in turn, gated by the complementary storage node on the opposite side of the cell. The gate electrode of each of the two data state control transistors is also connected to the drain electrode of a transistor of a cross-coupled transistor pair. Each of two transistors of this cross-coupled transistor pair has its gate electrode cross-coupled to the drain electrode of the other transistor and its source electrode connected to the power supply rail.

Gate processor arrangement for simulation processor system

Abstract: A gate processor arrangement for a logic simulation processor system includes a new event buffer memory (500c) for storing an event at a timing ta for a predetermined logic element in a section of a logic network; a fanout device (500d) for holding connection information for the predetermined logic element in the section of the logic network and reading the data of the predetermined logic element precedingly at a timing t, the input data of the predetermined logic element being changed at a timing "t+1"; and an evaluation gate buffer memory (500g) having a plurality of evaluation gate memory portions (500g₁, 500g₂) able to be connected with the fanout device and an evaluation device (500e). The arrangement also includes a net status memory (500f) for holding net status information corresponding to input data and output data of a predetermined logic element in the section of the logic network; and the said evaluation device (500e) responsive to the output of the evaluation gate buffer memory (500g) for reading the data in the net status memory (500f), generating information for the change of the network status at a timing "t+1", and supplying the generated information to an event transmission network (2) and/or the new event buffer memory (500c).

Full-level, fast CMOS output buffer

Abstract: An output buffer includes a pull-up circuit and a pull-down circuit for driving widely varying capacitive and inductive loads without significant output ringing. The pull-up circuit includes a first pull-up transistor (N2), a NAND logic gate (42) and a second pull-up transistor (P2). The pull-down circuit includes a first pull-down transistor (P3), a NOR logic gate (38) and a second pull-down transistor (N3). Output impedance is increased and energy stored in parasitic inductance is decreased by the pull-up and pull-down transistors so as to reduce significantly the inductive ringing while accelerating output transitions.

Binary logic level electrical detector namely to prevent the detection of secret codes contained in a memory card

Abstract: To prevent fraudulent action by ill-intentioned users, the detection of the secret codes, contained in a memory card with MOS integrated circuit and transmitted to an input/output unit, is prevented. This is done by interposing a read amplifier in the transmission chain, in the integrated circuit itself. This read amplifier essentially has two parallel-connected identical circuits, designed to take complementary logic states when they receive one and the same logic level to be detected. The result of this is that the electrical comsumption of the amplifier is the same regardless of the logic level transmitted. Thus, it becomes impossible to deduce the nature of the logic level transmitted. As an improvement, the outputs of the detector are provided with bistable circuits which are coupled to each other so as to be capable of taking transitory or spurious information detected into account.

A high packing density module generator for CMOS logic cells

Abstract: This paper presents new algorithms for cell pattern generation. The evaluated cell areas are based on measurements which are independent of production process technology. The placement algorithm recognizes logic gates from an unconstrained CMOS circuit diagram and places them in a pattern which minimizes the total wiring length. The generated cell pattern has bent gates and is grid-free. This generator has been applied to more than 60 cell designs used for industrial chips without the need of manual intervention.

Switch-Level Timing Simulation of MOS VLSI Circuits

Abstract: 1. Introduction.- 2. Overview of Simulation Techniques.- 2.1 Analog vs Digital Simulation.- 2.2 Gate-Level Simulation.- 2.3 Switch-Level Logic Simulation.- 2.4 Mixed-Mode or Hybrid Simulation.- 2.5 Switch-Level Timing Simulation.- 3. Mos Network Partitioning and Ordering.- 3.1 MOS Network Components and Models.- 3.2 Partitioning the MOS Network into Blocks.- 3.2.1 Review of Graph Theory.- 3.2.2 Blocks of an MOS Network.- 3.2.3 Partitioning Algorithm and Its Complexity.- 3.2.4 A CMOS Example.- 3.3* Partitioning into Driver and Pass Transistors.- 3.3.1 Motivation.- 3.3.2 Formal Definitions.- 3.3.3 Partitioning Algorithm.- 3.3.4 An NMOS Example.- 3.3.5 Modifications for CMOS Circuits.- 3.4 Ordering of Partitioned Blocks.- 3.4.1 Directed Graphs.- 3.4.2 Presence of Feedback and Its Detection.- 3.4.3 An Example to Illustrate Ordering.- 3.5 Conclusions.- 4. Switch-Level Timing Simulation.- 4.1 Overview.- 4.2 Waveform Representation.- 4.3 Simulation Algorithm.- 4.4 Deriving Inverter Voltage Equations.- 4.4.1 Equations for Switching Inputs.- 4.4.2 Equations for Fixed Inputs.- 4.4.3 Using the Equations.- 4.5 Determining the dc Output Voltage.- 4.6 Mapping Complex Blocks to Primitives.- 4.6.1 Transistor Reduction Basis.- 4.6.2 Subcircuit Reduction Algorithm.- 4.7 Parasitics.- 4.8 Sample Subcircuit Processing.- 4.8.1 Simple CMOS Inverter.- 4.8.2 CMOS NAND Gate.- 4.8.3 NMOS Inverter Driving a Pass Transistor.- 5. Simulating Strongly Connected Components.- 5.1 Waveform Relaxation vs Time-point Relaxation.- 5.2 Dynamic Windowing.- 6. Performance of Idsim2.- References.- About The Authors.

High density EEPROM cell and process for making the cell

Abstract: Disclosed is a stacked gate electrically erasable programmable read only memory EEPROM cell which utilizes a floating region and a common pass transistor to provide a cell which is programmable at a relatively low drain voltage and which, in addition, by utilizing a pass transistor, overcomes the programming disturbance and false read problems associated with typical stacked gate memory cells. The cell is constructed such that programming and erasing functions take place at separate locations in the gate oxide. An EEPROM memory cell array, utilizing the above memory cell, is disclosed which provides the ability to achieve both byte erase and block erase as well as byte write capability. Also disclosed is a process for producing such a memory cell and memory array.

Low voltage non-saturating logic circuit technology

Abstract: Digital logic circuitry designed to operate on a low voltage power supply without substantial transistor saturation thereby achieving lower power and higher opeational speeds. A non-saturating inverter with a low voltage swing can be made with one transistor using standard bipolar production processes and without clamp diodes. The novel circuitry uses logic units which can be modularly combined to form various other logical functions such as inverters, gates, flip-flops, etc. The preferred logic units use a transistor with the base connected by a load resistor to a first current network. The logical input is between the load resistor and base. The emitter is connected either directly or via one or more resistors to a second current network. The first and second power networks are constructed and arranged to provide a voltage-varying profile across both networks which are preferably complementary to provide nearly constant differential voltages across the logic units. The differential voltages can be relatively low, such as less than 1 volt, thus providing low power operation. The power networks provide the biasing voltage for the logic units without separate biasing circuitry. The inverters, gates or other logical units are advantageously grouped into current balanced groups which conduct approximatley constant current between the power networks for a variety of logical code combinations. The total current flow is preferably balanced to be approximatley constant. A means for providing a relatively fixed amount of current matched to equal the balanced total current flow for the logic array is also preferably used. Also disclosed are preferred power networks, logic signal interconnect methods, a preferred gate array and methods for operating such circuits in non-saturating manners.

A new layout optimization methodology for CMOS complex gates

Abstract: Efficient algorithms for the layout generation of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples are given showing that this approach can achieve a considerable improvement over previous ones. >

Analysis and synthesis of combinational pass transistor circuits

Abstract: A method for analyzing a wide range of CMOS pass transistor circuits is presented. Based on concepts derived from analysis, synthesis algorithms are proposed. They have been implemented as a program called PAVOS which can solve relatively complex problems. A manual method is presented for handling simpler ones. An effective minimization of the circuit area is obtained by using incomplete transmission gates, i.e. gates composed of either PMOS or NMOS transistors, without degrading the circuit output signals. The specification or a circuit can contain high-impedance states and attractive don't-cares called don't-happen states. It is shown that well-known good-pass transistor circuits, which synthesize results from designers' experience and intuition, can easily be obtained with the described methods. It is suggested that synthesis algorithms for all kinds of logics can be obtained by making small modifications on PAVOS. >

Fast, low noise cmos output buffer

Abstract: A CMOS output buffer (10) includes a transient pull-up circuit (14), a transient pull-down circuit (16) and a keeper circuit (12). The pull-up circuit (14) is responsive to a high drive enable pulse signal (HENB) for generating a transition from a low logic level to a high logic level at an output node (W). The pull-down circuit (16) is responsive to a low drive enable pulse signal (LENB) for generating a transition from the high logic level to the low logic level at the output node (W). The keeper circuit (12) is responsive to the high and low drive enable pulse signals (HENB, LENB) so as to maintain the output node (W) at the high logic level after the output node (W) has made the low-to-high transition and to maintain the output node (W) at the low logic level after the output node (W) has made the high-to-low transition. The CMOS output buffer (10) has a high speed of operation and has a high immunity to noise.

Bit line sense amplifier for programmable logic devices

Abstract: In a programmable logic device, switching speed is improved by preventing the bit line potential from going excessively close to ground even when large numbers of word line connections to the ground conductor are made. In addition, bit line pull up to logic 1 is effected more rapidly (without retarding bit line pull down to logic 0) by having two transistors connected in parallel with one another between the reference potential source and the bit line. One of these transistors is on all the time providing a relatively small leakage current. The other transistor is on only while the bit line is at logic 0, thereby speeding pull up to logic 1 and then shutting off so as not to impede subsequent return to logic 0.

Testable LSI device incorporating latch/shift registers and method of testing the same

Abstract: A testable LSI chip incorporating memory blocks, such as RAM and ROM, and random logic circuitry, and a testing method thereof are disclosed. A front-stage peripheral logic circuit block and rear-stage peripheral logic circuit block connected to the input and output modes of a memory block are provided on their output side and input side, respectively, with the flip-flops in correspondence to the input and output nodes of the memory block. The flip-flops on the output side and flip-flops on the input side are each connected to form a shift register. In testing the front peripheral logic block, the test result is latched in the flip-flops on the output side and then the contents are shifted out for reading. In testing the rear-stage peripheral logic circuit block, a bit pattern for testing is shifted-in and latched in the flip-flops on the input side and then supplied to the rear-stage peripheral logic circuit block under test. The front and rear-stage peripheral logic circuit blocks are tested independently of the memory block.

Logic circuit connecting input and output signal lines

Abstract: This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Advanced ECL with new active pull-down emitter-followers

Abstract: Approaches to high-speed and high-load driving capability of bipolar logic gates are discussed. Several circuits are investigated. It is shown that the Emitter Coupled Logic (ECL) with FET pull-down emitter-followers has a 3-5 times greater capability of driving capacitive loads than the conventional one. The performance improvement is drastically enhanced when applied to GaAs LSIs. >