Showing papers on "Pass transistor logic published in 1992"

Majority gates vs. general weighted threshold gates

Abstract: Small-depth circuits that contain threshold gates (with or without weights) and parity gates are studied. All circuits considered are of polynomial size. Several results that complete the work of characterizing possible inclusions between many classes defined by small-depth circuits are proved. >

CMOS Logic Circuit Design

Abstract: From the Publisher: CMOS Logic Circuit Design is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits It is a self- contained treatment that covers all of the important digital circuit design styles found in modern CMOS chips Introductory chapters on MOSFET physics and CMOS fabrication provide the background needed for a solid understanding of the circuit design techniques in the remainder of the book Static CMOS logic design is given an in-depth treatment which covers both the analysis and design of these types of circuits Emphasis is on analyzing circuits to understand the relationship between the design and performance in an integrated environment Analytic models and their application are presented to provide a uniform base for the design philosophy developed in the study Dynamic circuit concepts such as charge sharing and charge leakage are presented in detail and then applied to dynamic logic families such as domino cascades, self-resetting logic, and dynamic single-phase designs Differential logic families are given an entire chapter that discusses CVSL, CPL, and related design styles Chip issues such as interconnect modeling, crosstalk, and input/output circuits round out the coverage

Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing Information

Abstract: A new CMOS logic family allows the design of digital computing circuits that are more energy efJicient than conventional CMOS circuits, and that become increasingly energy efficient the slower they are operated. 7ke properties of the new logic family support Landauer’s thermodynamically motivated conjecture that the only necessarily dissipative opertion in compution is the erasure of information. Also, they suggest that there is an analogous result in switching theory, which bounds below the energy dissipation in circuits containing feedback. In this paper, we sketch the principles of the new logic family, and discuss some intuitive insights which might be useful in constructing a rigorous proof of a switching-theoretic analog of Landuaer’s principle.

Logic cell for field programmable gate array having optional internal feedback and optional cascade

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

The effect of logic block architecture on FPGA performance

Abstract: This authors explore the effect of logic block architecture on the speed of a field-programmable gate array (FPGA). Four classes of logic block architecture are investigated: NAND gates, multiplexer configurations, lookup tables, and wide-input AND-OR gates. An experimental approach is taken, in which each of a set of benchmark logic circuits is synthesized into FPGAs that use different logic blocks. The speed of the resulting FPGA implementations using each logic block is measured. While the results depend on the delay of the programmable routing, experiments indicate that five- and six-input lookup tables and certain multiplexer configurations produce the lowest total delay over realistic values of routing delay. The fine grain blocks, such as the two-input NAND gate, exhibit poor performance because these gates require many levels of logic block to implement the circuits and hence require a large routing delay. >

Automatic gate-level synthesis of speed-independent circuits

Abstract: In this paper, we present a CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates. The synthesized circuits are speed-independent; that is, they work correctly regardless of individual gate delays. We present synthesis results for a variety of specifications taken from industry and previously published examples. We compare our speed-independent circuits with those non-speedindependent circuits synthesized using the algorithms described in [I], in which delay elements are added to remove circuit hazardr. These synthesis results show that our circuits are on average approximately 25% faster with an area penalty of only IS%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efJrcient circuits compared to those synthesized with timing constraints.

Fast sense amplifier

Abstract: An integrated circuit sense amplifier includes a pair of complementary inputs for receiving a pair of complementary data signals which are input to a CMOS flip-flop having its output nodes connected to a logic low through a first transistor and its high side connected to a logic high through a second transistor. The first transistor is on when data signals are not being sensed, holding the nodes in a no-current, logic low state. The first transistor turns off and the second transistor turns on just prior to the arrival of a signal, precharging the nodes to an intermediate voltage, permitting the flip-flop to latch more quickly to a full-logic output when the signal arrives. A preamp may be interposed between the complementary inputs and the latch. The preamp inputs and outputs are precharged to voltage levels near or between their anticipated final levels, so that they reach their final levels quickly when the data signal arrives. The flip-flop output nodes may be connected to a tristate output circuit, which is also precharged to an intermediate level, enabling it to reach its full output more quickly.

Architecture of a CMOS fuzzy logic controller with optimized memory organisation and operator design

Abstract: A fuzzy logic control (FLC) unit as an on-chip part of a multi-purpose controller device is described. The architecture of the FLC is presented. The focus is on a method to implement the rule memory in a minimal memory space. A systematic analysis of the implementation of fuzzy MIN- or MAX-operators in digital CMOS circuits is included. A solution with minimal transistor count and maximal speed was found. >

Compact logic cell for field programmable gate array chip

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources. A novel reset circuit allows only the cells used as sequential elements to be reset, and only when reset would not cause contention with an input data signal.

Programmable interconnect structure for logic blocks

Abstract: A structure for making programmable connections (X) between the input (I0-I7) and (O0-07) output terminals of individual logic (20, 21) blocks in a logic device is disclosed. In one embodiment, each output terminal (O0-07) is programmably connected to only one input terminal (I0-I7) of each logic block (20, 21). The same principle is followed in making connections between the input pins of the device and the input terminals of the logic blocks.

Clocking systems and methods for pipelined self-timed dynamic logic circuits

Abstract: Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed

Programmable CMOS flip-flop emptying multiplexers

Abstract: A CMOS flip-flop circuit that includes master and slave inverter latches, a pass transistor for opening and closing access of the master latch input to an input signal D, and a special driver circuit between the master and slave latches to pull the input of the slave latch either up or down depending on the logic level of the master latch output. The pass transistor and driver circuit are responsive to a control signal, supplied by complementary clock signals or by multiplexers that select either the clock signals or a fixed logic high signal, to activate a conductive path to the inputs of respective master and slave latches. The driver circuit includes four transistors connected, so that first and second transistors are in series and third and fourth transistors are in series, to form two parallel paths from two logic level sources to the slave latch input. First and third transistors are driven by the master latch output, while second and fourth transistors are driven by the control signal to the drive circuit. The two logic level sources connected to the first and third transistors may be fixed logic high and low voltage levels for conventional flip-flop operation or to multiplexers, each selecting either a logic high or a logic low voltage level, for programmable polarity of the flip-flop output. Placing latches enabled by the pass transistor control signal between the multiplexers and the first and third transistors and increasing the selection of the multiplexers to include complementary slave latch output feedback signals provides programmable D-type or toggle flip-flop operation. The multiplexer's nontoggle selection signal may be fixed or dynamically variable through a configuration multiplexer for dynamic polarity of the flip-flop's output.

Low voltage input and output circuits with overvoltage protection

Abstract: An input stage suitable for use with any desired supply voltage VCC, including supply voltages less than 5 volts, and which is capable of withstanding an overvoltage input signal greater than VCC applied to its input pad. A pass transistor is used between the input pad and the input buffer in order to limit the voltage supplied to the input buffer, thereby allowing voltages in excess of VCC to serve as a legitimate logical one input signal to the input buffer. Overvoltage protection is used to limit the voltage on the input pad to a voltage in excess of the greater-than-VCC legitimate input voltage. An output stage is suitable for use with a wide variety of supply voltages, including supply voltages less than 5 volts, while allowing proper operation in the event that a legitimate overvoltage is applied to its output pad. ESD protection is provided in order to limit the voltage on the output pad to a voltage greater than the maximum legitimate overvoltage. Cascode devices are used to limit the voltages seen by the pull up and pull down transistors when a legitimate overvoltage is applied to the output pad. Suitable transistor switches are used to prevent excessive current from being dissipated when a legitimate overvoltage is externally applied to the output pad when the output stage is in either the high impedance mode or the active high mode.

Programmable fuzzy logic circuits

Abstract: A fuzzy logic circuit for operating a fuzzy logic with "fuzziness" taken into account has an operation section memory unit in which the result of operation to be outputted in response to an input is stored in an address specified by the input, the result of operation being rewritable, whereby the change in the contents of a fuzzy logic operation to be performed can be handled merely by rewriting the contents of the operation section memory unit.

Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections

Abstract: We have developed a new binary-logic circuit scheme in which a highly-functional device called a neuron MOS transistor (vMOS) is utilized as a key component A dramatic reduction in the number of transistors as well as in the complexity of interconnections has been achieved by the new circuit configuration using vMOS Operational principles and design techniques of vMOS binary-logic circuits are described The operation of the designed circuits has been experimentally verified by fabricating test circuits using a standard double-polysilicon CMOS process >

Design of static CMOS self-checking circuits using built-in current sensing

Abstract: The authors present a novel scheme for implementing self-checking circuits in static CMOS. A strongly code disjoint (SCD) built-in current sensor (BICS) is presented. It is used to cover faults whose detection cannot be guaranteed by logic monitoring. A previously fabricated and tested high-speed BICS is examined for its behavior in the presence of faults. Then, a self-exercising mechanism is designed to obtain the SCD property. The integration of this SCD BICS with a self-checking circuit achieves the well-known goal of total self-checking. >

Method for disguising a microelectronic integrated digital logic

Abstract: Focussed ion beam (FIB) implants (38,40) are used to set the threshold voltages of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a selected logic gate (34,36) in a microelectronic integrated digital logic circuit (31) such that the direct current (DC) transfer function and logic thresholds are essentially the same as for another logic gate (30,32) which is not altered by FIB implants, but the switching speed is greatly reduced. This causes the altered gate (34,36) to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered or disguised gate (34,36) is thereby always on or always off at the normal operating speed, whereas the unaltered gate (30,32) switches in the normal manner. This impedes attempts at reverse engineering since the circuit (31) operates differently under test and operating conditions, and the true logic functions of the gate (34,36) cannot be determined by known low speed test procedures.

Recovering phase and data from distorted duty cycles caused by ECL-to-CMOS translator

Abstract: A logic interface circuit for recovering phase and data information from ECL differential input signals of the NRZI type having distorted duty cycles caused by ECL-to-CMOS translators includes first and second ECL-to-CMOS translators (T1, T2), first and second delay circuits, and an output logic circuit The first delay circuit is formed of a first inverter (I1), a first delay network (D1), and a first NAND logic gate (N1). The second delay network includes a second inverter (I2), a second delay network (D2), and a second NAND logic gate (N2). The output logic circuit is formed of a third NAND logic gate. The interface circuit generates an output signal which is in the form of a pulse train whose cycle time can be detected for determining the frequency information and whose presence or absence of pulses can be detected for determining data information.

Digital ECL bipolar logic gates suitable for low-voltage operation

Abstract: Several digital bipolar logic circuits are described, for applications as digital logic gates and for buffering and level-shifting. These circuits are adapted for high-speed operation, and they have reduced supply-voltage requirements. In each of these circuits, a control device such as a transistor turns an input circuit on or off by means of an emitter-to-emitter connection. However, unlike most conventional ECL circuits, these circuits avoid stacked transistor configurations.

Logic macro and protocol for reduced power consumption during idle state

Abstract: A control circuit and protocol are disclosed for an integrated circuit (such as a static PLA) wherein standby power is minimized during an idle processor state condition without loss of circuit outputs. For static PLAs, control circuits shutoff any active current path and drive the logic array outputs to zero whenever an idle state condition exists. Inputs to the logic array are held in static latches associated with the static PLA. The novel halt protocol includes: powering-down the logic macro upon initiation of an idle state by halting all internal clocks and then decoupling the logic array from power supply voltage VDD. Circuit power-up includes reactivating the logic array by first coupling the array to supply voltage VDD and allowing sufficient time for the outputs of the array and any associated logic to stabilize; and then restarting the previously halted internal clocks. Analogous techniques are also described for dynamic PLAs.

CMOS clocked logic decoder

Abstract: The present semiconductor logic circuit includes a first-stage logic circuit section comprising of a first precharging transistor, a first grounding transistor, and a first logic element and a second-stage logic circuit section comprising of a second precharging transistor, a second grounding transistor, and a second logic element. The first precharging transistor has the common terminal connected to a power terminal and receives a clock signal at the input terminal. The first grounding transistor has the common terminal connected to the ground and receives a clock signal at the input terminal. The first logic element has the grounding end connected to the output terminal of the first grounding transistor and the output end connected to the output terminal of the first precharging transistor. The second precharging transistor has the common terminal connected to a power terminal and the input terminal connected to the output end of the first logic element. The second grounding transistor has the common terminal connected to the ground and the input terminal connected to the output end of the first logic element. The second logic element has the grounding end connected to the output terminal of the second grounding transistor and the output end connected to the output terminal of the second precharging transistor.

Single event upset immune logic family

Abstract: A complete logic family which is SEU immune is constructed, using logic/circuit design techniques, to recover from an SEU, regardless of the shape of the upsetting event. The logic family provides a redundancy of data to be used to restore data lost by an SEU. Two transistor networks are used, a p-channel network and an n-channel network. Each transistor network consists of a plurality of input transistors and a feedback transistor. The feedback transistor is sized to be weak compared to the input transistors. The transistor networks are designed to either resist an SEU or to shutdown until the SEU is over and then the network which is not shutdown will restore the data of the network that was hit by the SEU. The logic family can prevent glitch propagation from an upset node and can be implemented in a standard, commercial CMOS process without any additional processing steps. The logic family includes but is not limited to an Inverter, 2-input Nand, 2-input Nor, 3-input OrNand and a 3-input AndNor. The SEU recovery mechanism used by the logic family can be extended to logic structures in general. The SEU recovery mechanism is independent of the duration or shape of the upsetting event.

Ultrafast digital soliton logic gates

Abstract: We demonstrate all-optical fibre switches, including soliton-dragging logic gates, soliton-interaction gates and soliton-trapping AND-gates, that have the potential of operating up to speeds of 0.2 Tbps. Solitons in fibres are attractive for ultrafast timedomain switching because they avoid pulse distortion during propagation and because they exhibit particle-like properties. Soliton-dragging logic gates satisfy all requirements for a digital optical processor and having switching energies approaching 1 pJ. In addition, soliton-dragging logic gates are one example of a more general timedomain chirp switch architecture in which a dispersive delay line acts as a ‘lever-arm’ to reduce the switching energy. Soliton-interaction gates are based on elastic collisions between solitons and illustrate that solitons can be used to implement conservative, billiard-ball logic operations. Soliton-trapping AND-gates are sensitive to the timing of the input pulses and display on/off contrast ratios greater than 20∶1. The soliton-trapping AND-gate can serve as the final stage in an all-optical system and as the interface to electronics. These ultrafast gates may prove advantageous in applications where the switch bandwidth limits the performance of the system

Output logic macrocell with enhanced functional capabilities

Abstract: An output logic macrocell ('OLMC' 30a) containing an exclusive OR gate (309a) is associated with the product terms (P) and other outputs of a logic block such as a programmable logic array. The OLMC (30a) is capable of providing enhanced functions, including cascaded exclusive OR gates, function sharing, T and J-K flip-flop emulation, asynchronous clocking, and reset selection. In addition, a logic block is used as the source of an asynchronous clock pulse and is connected to the global clock distribution system (320a) of a device such as a high density programmable logic device.

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

Abstract: An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward. >

Enhancement source-coupled logic for mixed-mode VLSI circuits

Abstract: Low-noise enhancement source-coupled logic (ESCL) is proposed for applications in high-precision mixed-mode integrated circuits (ICs). The differential ESCL topology offers potential low-power supply noise advantages over conventional CMOS logic for mixed-mode ICs by steering a constant current to perform the logic operation and it requires a smaller logic swing ( Delta V/sub L/ >

Integrated circuit having alternate rows of logic cells and I/O cells

Abstract: A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.

Transition detection circuit

Abstract: A circuit for detecting the transition of the state of logic signals at a plurality of input terminals is provided. The circuit has a transition detecting block connected to each input terminal which generates a pulse at the transition of a logic signal at the input terminal, an OR logic block connected to each transition detecting block for generating a combined logic signal from the transition detecting blocks, and a latch having SET and RESET input nodes and an output node. The SET input node is connected to the OR logic block so that the output node switches into a first logic state from a second logic state responsive to the combined logic signal on the SET input node. The circuit also has a delay unit connected to the OR logic block and to the RESET input node of the latch which precisely delays the combined logic signal to the RESET input node so that the output node of the latch switches back to the second logic state. A pulse is thus generated at the output node responsive to logic signal transitions at the input terminals. The pulse has a width controlled by the delay unit.

Integrated logic circuit with functionally flexible input/output macrocells

Abstract: An integrated circuit package including a plurality of macrocells for connecting a logic circuit of the package to a plurality of external contacts of the package. At least one of the macrocells has an output driver that is enabled or disabled by a control signal for transmitting or preventing transmission of a logic signal to one of the contacts. The control signal is generated by a logic gate that receives and logically combines an individual output enable signal dedicated to that particular macrocell with a selected signal. One signal that may be selected is a regional output enable signal that is supplied to more than one macrocell. Each macrocell also has a feedback multiplexer selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal, a stored logic signal from a flip-flop register in the macrocell, a signal applied to the external contact associated with that macrocell, and a signal applied to another external contact associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers in two different macrocells, and at least one contact connects in this manner to separate logic regions of the logic circuit. The flip-flop register in the macrocell has a choice of data inputs selected by another multiplexer from among at least one logic signal from the logic circuit and at least one signal applied to an external contact.

Analysis of crosstalk interference in CMOS integrated circuits

Abstract: The authors show how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behavior by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed, and the influence of crosstalk on the behavior of basic functions such as logic gates, latches, RAM memory, and analog-to-digital converters is evaluated. >