Showing papers on "Pass transistor logic published in 1994"

Precomputation-based sequential logic optimization for low power

Abstract: We address the problem of optimizing logic-level sequential circuits for low power We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle We present two different precomputation architectures which exploit this observation The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions If the output values can be precomputed, the original logic circuit can be "turned off" in the next clock cycle and will have substantially reduced switching activity The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation We present experimental results on various sequential circuits Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay >

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Abstract: The two-dimensional discrete cosine transform (2D DCT) has been widely recognized as a key processing unit for image data compression/decompression. In this paper, the implementation of a 200 MHz 13.3 mm/sup 2/ 8/spl times/8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 /spl mu/m base-rule CMOS technology and 0.5 /spl mu/m MOSFET's, performs the DCT processing with 1 sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-F/F) circuit technique in combination with nMOS differential logic. The SA-F/F, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dual-rail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation. >

Current-mode CMOS multiple-valued logic circuits

Abstract: Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >

Noise in digital dynamic CMOS circuits

Abstract: Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits. >

Adiabatic Computing with the 2n-2n2d Logic Family

Abstract: Low-energy computing is an idea whose time has come. Applications include the smallest systems (where battery size and weight are crucial) as well as the largest systems (where power supply and cooling are crucial). To turn an F E T on or off requires transferring a certain amount of energy (the switching energy). The energy dissipated during this transfer need not be related to the energy transferred, but in ordinary CMOS logic circuits both quantities are on the order of $CV,2,, where C is the capacitance of a typical node, and V d d is the operating voltage. This level of dissipation is unavoidable if a l l the needed electrons are extracted from the V d d terminal of the power supply and ret,urned to the ground terminal. The essential idea of adiabatic computing is to construct circuits that allow each needed electron to be extracted at the lowest feasible voltage and returned at the highest feasible voltage. Ramp-like power/clock signals are required. Obviously it is advantageous to reduce c and V d d , but there are limits; in any case for the purposes of this paper we take such reductions for granted and show how dissipation can be further reduced at any particular V d d and c. The theoretical limit on dissipation is 0 for logically reversible operations, and kT for logically irreversible operations (1). Since kT is six or seven orders of magnitude below present-day values of $CV2d, there is considerable room for compromise. The logic family considered here, which we call 2N-2N2D, emphasizes overall system feasibility and throughput, while providing energy savings of “only” half an order of magnitude or so. Unlike previous diode-based energy recovery schemes (2; 3; 4) our major design goal was to present a nearly constant, data-independent capacitive load to the clock even though it makes 2N-2N2D about twice as complex as 1T1D (4). Constant load is vital, permitting operation from “stored energy” clock drivers. We have detailed simulations of such a clock driving a 6000-bit 2N-2N2D shift register ring, recovering over 75% of the transferred energy.

Supercomputing with spin-polarized single electrons in a quantum coupled architecture

Abstract: We describe a novel quantum technology for possible ultra-fast, ultra-dense and ultra-low-power supercomputing. The technology utilizes single electrons as binary logic devices in which the spin of the electron encodes the bit information. Both two-dimensional cellular automata and random wired logic can be realized by laying out on a wafer specific geometric patterns of quantum dots each hosting a single electron. Various types of logic gates, combinational circuits for arithmetic logic units, and sequential circuits for memory have been designed. The technology has many advantages such as (1) the absence of physical interconnects between devices (inter-device interaction is provided by quantum mechanical spin-spin coupling between single electrons in adjacent quantum dots), (2) ultra-fast switching times of approximately 1 picosecond for individual devices, (3) extremely high bit density approaching 10 terabits cm-2, (4) non-volatile memory, (5) robustness and possible room-temperature operation with very high noise margin and reliability, (6) a very low power delay product ( approximately 10-20 J) for switching between logic levels, and (7) a very small power dissipation of a few tens of nanowatts per switching event. In spite of the above advantages, the technology also has some serious drawbacks in that the fan-out of individual logic devices may be small, wiring crossover is very problematic and the devices themselves have no inherent gain so that isolation between input and output is virtually non-existent. These are problems that plague all similar quantum technologies although they are seldom recognized as such. We will discuss these problems, and where possible, offer plausible solutions. In spite of these drawbacks, however, there are still enough attractive features of this technology to merit serious research. In this paper, we will describe how the spin-polarized single-electron logic devices work, along with the associated circuits and architecture. Finally, we will propose a new fabrication technique for realizing these chips which we believe is much more compatible with the demands of the technology than conventional nanofabrication methods.

Inverter models of CMOS gates for supply current and delay evaluation

Abstract: The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well. >

Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers

Abstract: A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Some of the programmable logic is used to selectively connect logic array block input terminals to the horizontal conductors. Additional logic in each column is used to selectively connect the horizontal conductors to either logic array block output terminals from the same column or logic array block output terminals from an adjacent column. The additional logic prevents certain interconnection pathways from being blocked and increases the overall flexibility of the interconnection scheme of the programmable logic device, thereby improving device performance.

Asymptotically zero energy computing using split-level charge recovery logic

Abstract: The dynamic dissipation of CMOS circuits is becoming a major concern for designers of personal information systems and large computers Here, we present new CMOS logic families, including Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically, thus having a power consumption that drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS The technique in these new families rely on explicitly reversible pipelined logic gates to provide the necessary information needed to recover most of the energy used in the computation We report results of testing the first fully quasistatic 8x8 multiplier chip (SCRL-1)

Functions and applications of monostable-bistable transition logic elements (MOBILE's) having multiple-input terminals

Abstract: The MOBILE is a logic gate exploiting the monostable-bistable transition of a circuit that consists of two resonant tunneling transistors connected in series. It has several advantages including multiple inputs and multiple functions. This paper describes the output characteristics of multiple-input MOBILE's and discusses their applications. For a two-input MOBILE, it is demonstrated that both NAND and NOR operations are possible with the appropriate control voltage. This implies the possibility of a variable function logic gate. Furthermore, the threshold logic operations for a weighted sum of input signals are demonstrated for a three-input MOBILE with a weight ratio of 4:2:1. The applications of MOBILE's in parallel processing architectures such as cellular automata and cellular neural networks are discussed based on the above results. Circuit simulations using a simple model of resonant tunneling transistors successfully reproduce the basic characteristics of MOBILE's, and demonstrate the usefulness of MOBILE's in such applications. >

Short-circuit power dissipation estimation for CMOS logic gates

Abstract: Short-circuit power dissipation contributes significantly to the overall power dissipation in ICs. A new formula has been developed for the estimation of short-circuit power dissipation in CMOS logic gates based on the /spl alpha/-power law model that includes velocity saturation effects of short channel MOSFETs. A technique is developed for the measurement of short-circuit current and power dissipation of CMOS logic gates for use in circuit simulation. SPICE simulation results show that the new formula is significantly more accurate than existing formulae. >

Field programmable logic device with dynamic interconnections to a dynamic logic core

Abstract: The architecture, operation and design of a novel Field Programmable Logic Device is described. The device (20) implements a circuit by using a dynamic logic core (22) that executes staged logic corresponding to the logic levels of the implemented circuit. Logic inputs to the dynamic logic core are obtained from a dynamic interconnection array (26). Appropriate logic inputs for a given logic level are dynamically selected and routed by the dynamic interconnection array (26). When necessary, the dynamic interconnection array (26) buffers signals which are required at subsequent logic levels. The dynamic interconnection array (26) selects logic inputs for a given logic level from circuit input signals, buffered signals and dynamic logic core output signals.

Estimation of circuit activity considering signal correlations and simultaneous switching

Abstract: This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results.

Reversible logic issues in adiabatic CMOS

Abstract: Power dissipation in CMOS circuits has become increasingly important for the design of portable, embedded and high-performance computing systems. Our VLSI research group has investigated a novel form of energy-conserving logic suitable for CMOS. Through small chip-building experiments, we have demonstrated the low-power operation of simple logic functions. These chips have used logical reversibility on a small, sometimes trivial, scale to achieve their low-power operation. In moving towards more complex functions, the role of reversibility will increase. This paper addresses two problem areas that we have found to be crucial to successfully realizing low-power operation of CMOS chips using reversible logic techniques. The first area is the energy-efficient design of the combined power supply and clock generator. The second is the logical overhead needed to support reversible logic functions. The first problem area, though formidable, seems amenable to systematic approaches. Significant inroads have been made towards finding practical, efficient solutions. The second, however, appears to be by far the more difficult hurdle to overcome irreversible logic is to become an attractive approach for reducing power dissipation in CMOS. >

Field-programmable gate array

Abstract: A field-programmable gate array comprises regularly arrayed logic elements, a first group of signal lines interconnecting the logic elements adjacent to each other, and a second group of signal lines interconnecting the logic elements not adjacent to each other to provide a field-programmable gate array capable of forming an adder, logic operation unit, or the like having a high utilization of logic elements.

Integrated circuit having different power supplies for increased output voltage range while retaining small device geometries

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit. The output multiplexer includes an n-channel pass transistor and a p-channel pass transistor coupled to the output terminal in parallel with each other and responsive to the control signal for passing one or the other of the dual analog signals to the output terminal. Exposure of the pass transistors to voltages exceeding the safe operating voltage is avoided by inserting shielding transistors in series therewith.

Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays

Abstract: Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays (10), without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip-flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) (10) is preserved by clustering together in the mask-configured integrated circuit (a gate array) (16) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area.

Precomputation-based sequential logic optimization for low power

Abstract: We address the problem of optimizing logic-level sequential circuits for low power We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle We present two different precomputation architectures which exploit this observationWe present an automatic method of synthesizing precomputational logic so as to achieve maximal reductions in power dissipation We present experimental results on various sequential circuits Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay

Logic synthesis for field-programmable gate arrays

Abstract: In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices. >

The future of programmable logic and its impact on digital system design

Abstract: Field programmable gate arrays (FPGAs) combine the high-integration benefits of gate arrays with the time-to-market benefits of a user-programmable device. Already a mainstream logic technology, the growth rate of FPGA usage will continue to exceed that of other ASIC technologies. FPGA technology is having a major impact on electronic system design, especially through the use of FPGAs as reconfigurable computing elements. >

A high speed, low power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications

Abstract: Swing Restored Pass-transistor Logic (SRPL), a high speed, low power logic circuit technique for VLSI applications is described. By the use of a pass-transistor network to perform logic evaluation, and a latch type swing restoring circuit to drive gate outputs, this technique renders highly competitive circuit performance. An SRPL based multiply and accumulate circuit for multimedia applications is implemented in double metal 0.4 /spl mu/m CMOS technology. >

Low-pass filter for computing the transition density in digital circuits

Abstract: Estimating the power dissipation and the reliability of integrated circuits is a major concern of the semiconductor industry. Previously, we showed that a good measure of power dissipation and reliability is the extent of circuit switching activity, called the transition density (see ibid., vol. 12, no. 2, p. 310-23, 1993). However, the algorithm for computing the density in the afore-mentioned paper is very basic and does not take into account the effect of inertial delays of logic gates. Thus, as we will show in this paper, the transition density may be severely overestimated in high-frequency applications. To overcome this problem, we model the effect of gate delay on logic signals in the form of a conceptual low-pass filter module that does not allow unacceptably short logic pulses to propagate. Using a stochastic model of logic signals, we then derive the equations required to propagate the transition density through the filter. We will present experimental results that illustrate the validity and importance of these results. >

200 MHz video compression macrocells using low-swing differential logic

Abstract: Improving the performance of fully dedicated macrocells is key to realizing HDTV-resolution video de/compression LSIs operating at more than 100 MHz, having reasonable power consumption and chip size small enough for consumer applications. Existing circuit techniques are either not sufficiently fast or are area consuming. However, these problems are overcome by using low-swing differential logic to realise such macrocells. >

CDMA base station modulator for digital cellular mobile communication systems

Abstract: A base station modulator for the digital cellular mobile communication system achieves reduced hardware complexity in a base band QPSK modulating circuit by applying the Multilevel Logic Operation (MLO) which is extended from the conventional binary exclusive-OR operation, to the conventional Base Station Modulator (BSM). The base station modulator includes a plurality of spreaders 621 for QPSK spreading of a voice data stream. These spreaders 621 employ binary-multilevel Logic (MLO) gates instead of multiple binary exclusive-OR gates. The binary-multilevel Logic gate includes a subtractor 510 and a selector 520. The subtractor has one input (-) to which multilevel logic values are applied and one input (+) to which a maximum logic level of the multilevel logic values is applied. The selector has one input to which the multilevel logic values are applied, one input to which the output signal of the subtractor 510 is applied, and one control input to which the binary logic value is applied. If the binary logic value is zero (0), the selector 520 selects and outputs the multilevel logic values, and if the binary logic value is one (1), the selector 520 selects and outputs the output signal from the subtractor 510.

Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage

Abstract: A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

CMOS logic circuits having low and high-threshold voltage transistors

Abstract: A logic circuit includes a low-threshold logic circuit, a pair of first and second power lines, a first dummy power line, and a first high-frequency logic circuit. The low-threshold logic circuit has a logic circuit element constituted by a plurality of low-threshold field effect transistors. The pair of first and second power lines supply power to the low-threshold logic circuit. The first dummy power line is connected to one of power source terminals of the low-threshold logic circuit. The first high-threshold control transistor is arranged between the first dummy power line and the first power line.

Rectification of Multiple Logic Design Errors in Multiple Output Circuits

Abstract: This paper presents the EXMalgorithm, which locates multiple logic design errors in a combinational circuit with multiple output. An error possibility index and a six-valued simulation method have been introduced to reduce the number of error candidates without missing real errors. Experimental results have shown that this algorithm locates all errors at high hit ratio for benchmark circuits.

Select set-based technology mapping method and apparatus

Abstract: A logic circuit is implemented on a macrocell of a field programmable device using select sets of a logic function which represents a transformation of the one or more input signals of the logic circuit to the output signal of the logic circuit. Select sets of a logic function are determined (i) by grouping input signals which correspond to equal co-factors of the logic function or (ii) by grouping input signals such that one input signal of a group never appears in a term of the logic function in a greedy phase-minimized RMF canonical form without all other input signals of the group. The logic circuit is implemented on a macrocell which includes a circuit element which selects one of two or more input signals according to one or more select signals, each of which is driven by a respective logic gate. Examples of such circuit elements include multiplexers and random access memory (RAM). The logic circuit is implemented by placing on input lines of a logic gate driving a select line the input signals or the complement of the input signals of a select set.

A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays

Abstract: This paper introduces a new design approach that combines logic and layout synthesis for Cellular-Architecture (CA) FPGAs. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly-shaped multi-level structure of (mostly) locally connected cells. This two-dimensional array of logic cells is well suited for CA-type FPGA realization. Two stages: restricted factorization and technology folding are discussed in more details. The architecture constraints and the implementation are presented for ATMEL6000 series architecture.

Probability analysis for CMOS floating gate faults

Abstract: The electrical behavior of a floating gate MOS transistor is mask-topology-dependent, i.e. floating on different sites of interconnection may result in different fault behavior. In this paper, we present a net-oriented deterministic approach to compute the probability of different open faults on each net, by taking into account the process defect statistics and mask layout data. The open faults causing floating gates are classified into three types, i.e. (1) open causes floating gates of p-channel transistors, (2) open causes floating gates of n-channel transistors, and (3) open causes floating gates of both p-channel transistors and n-channel transistors. For each net the probabilities of floating gate faults (1), (2) and (3) are obtained. The results of the analysis can be used as guidelines for designing more reliable and testable circuits, adopting more accurate fault models, introducing effective testing strategies. >