Showing papers on "Pass transistor logic published in 1995"

CMOS Digital Integrated Circuits Analysis & Design

Abstract: CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testability. This book provides rigorous treatment of basic design concepts with detailed examples. It typically addresses both the computer-aided analysis issues and the design issues for most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the driving force behind the development of advanced computer hardware. Table of contents 1 Introduction 2 Fabrication of MOSFETS 3 MOS Transistor 4 Modeling of MOS Transistors Using SPICE 5 MOS Inverters: Static Characteristics 6 MOS Inverters: Switching Characteristics and Interconnect Effects 7 Combinational MOS Logic Circuits 8 Sequential MOS Logic Circuits 9 Dynamic Logic Circuits 10 Semiconductor Memories 11 Low-Power CMOS Logic Circuits 12 BiCMOS Logic Circuits 13 Chip Input and Output (I/O) Circuits 14 Design for Manufacturability 15 Design for Testability

Digital Integrated Circuits

Abstract: Partial table of contents: Properties and Definitions of Digital ICS. Diodes. Bipolar Junction Transistors. Diode-Transistor Logic (DTL). Schottky Transistor-Transistor (STTL). Other TTL Gates. Basic Emitter-Coupled Logic (ECL). MECL III and ECL 10K. Other ECL Gates. Introduction to MOS Digital Circuits. Resistor Loaded NMOS Inverter. Enhancement-Depletion Loaded NMOS Inverter. NMOS Gates. CMOS Inverter. CMOS Tri-State Gates. CMOS Drivers. Dynamic CMOS. BiCMOS. Latches and Flip-Flops. Semiconductor Read-Only Memories. Direct Coupled NMESFET Logic (DCFL) Inverter. Schottky Diode NMESFET Logic (SDFL) Inverter. Other Gallium Arsenide Logic Family Inverters. Gallium Arsenide NMESFET Gates. Appendices. Supplementary Reading. Selected Answers. Index.

Logic Gates Made from Polymer Transistors and Their Use in Ring Oscillators

Abstract: Metal-insulator-semiconductor field-effect transistors have been fabricated from polymer semiconductors that can be processed from solution. The performance of these transistors is sufficient to allow the construction of simple logic gates that display voltage amplification. Successful coupling of these gates into ring oscillators demonstrates that these logic gates can switch subsequent gates and perform logic operations. The ability to perform logic operations is an essential requirement for the use of polymer-based transistors in low-cost low-end data storage applications.

Adiabatic dynamic logic

Abstract: With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 /spl mu/m CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry. >

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

Abstract: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

A time-multiplexed FPGA architecture for logic emulation

Abstract: This paper presents an architecture for a FPGA oriented towards logic emulation, to achieve maximum usable logic density per unit silicon area, and fast mapping. Logic circuits are translated into a program that is executed sequentially by a network of processor elements. Overall, a sevenfold increase in raw logic blocks, and a 25-fold increase in usable logic blocks compared to a FPGA-based logic emulator is expected for a given silicon area.

Interconnect architecture for field programmable gate array using variable length conductors

Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Logical operation circuit employing two-terminal chalcogenide switches

Abstract: A logic family employing a plurality of two-terminal chalcogenide switches as logic gates therein. Preferably the two-terminal chalcogenide switches are chalcogenide threshold switches. The logic can employ multi-phase clocking such as four-phase clocking.

Integrated power clock generators for low energy logic

Abstract: Low-energy (adiabatic) logic families have been proposed to reduce energy consumption of VLSI logic devices. Instead of the conventional DC power supply, these logic families require AC power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper, high-frequency resonant DC/AC inverters are proposed as power clock generators where all power switches and control circuitry are integrated on the same chip with low-energy logic. This results in better system efficiency and simpler power distribution. Closed-form results are derived to facilitate efficiency-optimized design of the proposed power clock generators. To illustrate system integration and energy savings, the optimized power clock is used to supply a novel clocked CMOS adiabatic logic (CAL). >

Magnetic spin transistor device, logic gate & method of operation

Abstract: A new magnetic spin transistor is provided. This spin transistor can be used as a memory element or logic gate, such as an OR, AND, NOT, NOR and NAND gate. The state of the magnetic spin transistor logic gate is set inductively. This new magnetic spin transistor/gate can be operated with current gain. Furthermore, inductive coupling permits the linking of multiple spin transistors and spin transistor gates to perform combinational tasks. A half adder embodiment is specifically described, and other logic gates and combinations of half adders can be constructed to perform arithmetic functions as part of a microprocessor.

Multiple-valued logic

Abstract: The ultimate usefulness of a number system depends on its implementation. Multiple-valued logic has been implemented in charge-coupled devices (CCD). In this technology, logic values are encoded as charge. For example, prototype four-valued logic devices have been implemented at the University of Twente (Enschede, Holland). Hitachi has implemented a 16-valued memory that stores the equivalent of 10/sup 6/ bits. CCD is more compact than any other VLSI technology. Although it is slower than CMOS (complementary metal oxide semiconductor), it is much faster than the disk and has the potential of replacing the disk. The use of multiple-valued logic in CCD increases its storage capacity significantly. Multiple-valued logic has also been implemented in current-mode CMOS. >

Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment

Abstract: Using a multiple-input high-functionality transistor neuron MOSFET (/spl nu/MOS), demonstrates a dramatic simplification of logic circuit configuration compared to conventional CMOS circuitry. The purpose of this paper is to present a new clocked /spl nu/MOS logic circuit scheme in which a clock-driven switching transistor attached to the floating gate is used not only to initialize the floating-gate charge but also to perform auto-adjusting of its inverting threshold that cancels the fluctuations arising from fabrication.

Programmable logic device with regional and universal signal routing

Abstract: A programmable logic device having a plurality of logic cells (151-15N) arranged in groups defining separate logic regions (111-11N), both regional (191-19N) and multi-regional (13) bus lines, and a crosspoint switch matrix (37) which serves only to route signals from bus lines (391-39J and 401-40L) to inputs of the logic cells (311-31J) without logically combining two or more of the bus signals, i.e. without forming product terms. Rather, all logic is carried out by the logic cells (311-31J) themselves. In particular, the switch matrix (37) is constructed so that each bus line (391-39J and 401-40L) can connect to one or more logic cell inputs, but each logic cell input can meaningfully connect to only one bus line without shorting. In one embodiment, each logic cell (311-31J) feeds one logic signal back (411-41J) to a regional bus line (191) and can potentially feed back another logic signal through its region's universal select matrix (47) to a universal bus line (13). The select matrix (47) connects a subset of the region's potential feedback signals to the universal bus (13).

Circuit for selecting a bit in a look-up table

Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

CMOS EEPROM cell with tunneling window in the read path

Abstract: A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.

High voltage cmos logic using low voltage cmos process

Abstract: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors (P1, N1) before the gate terminals of each input switching transistor (P2, N2). Each shielding transistor has a gate terminal coupled to a shield voltage (Vshld) of a magnitude substantially midway between ground potential and the positive power supply voltage. The input signal is conveyed by the source-drain channel of the input shielding transistor to the gate of the switching transistor.

Memory in a programmable logic device

Abstract: A programmable logic device includes a plurality of logic blocks coupled to an interconnect matrix, wherein one of the plurality of logic blocks comprises configurable memory logic having control logic coupled to a storage element. The control logic receives a plurality of control signals from the interconnect matrix and performs substantially all logic functions required for the configurable memory logic to selectively function as each of a plurality of memory devices. The plurality of memory devices includes a first-in-first-out (FIFO) memory device, a last-in-first-out (LIFO) memory device, a single-port memory device (e.g. single-port SRAM) and a multi-port memory device (e.g. dual-port RAM). Additionally, multiple logic blocks may comprise configurable memory logic. Each logic block may perform a different memory function. These logic blocks can be cascaded together to form memory devices with greater memory depths and/or widths than possible with a single logic block with configurable memory logic.

Fundamentals of electrical engineering

Abstract: PART I: CIRCUITS 1 Basic Elements and Laws 11 Voltage Sources, Current Sources, and Resistors 12 Kirchhoff's Current Law (KCL) 13 Kirchhoff's Voltage Law (KVL) 14 Independent and Dependent Souces 15 Instantaneous Power 2 Circuit Analysis Principles 21 Nodal Analysis 22 Determinants and Cramer's Rule 23 Mesh Analysis 24 Ideal Amplifiers 25 Thevevnin's and Norton's Theorems 26 Linearity and Superposition 3 Time-Domain Circuit Analysis 31 Inductors and Capacitors 32 Integral Relationships for Inductors and Capacitors 33 First-Order Circuits - The Natural Response 34 First-Order Circuits - The Complete Response 35 Second-Order Circuits - The Natural Response 36 Second-Order Circuits - The Complete Response 4 AC Analysis 41 Time-Domain Analysis 42 Complex Numbers 43 Frequency-Domain Analysis 44 Power 45 Important Power Concepts 46 Polyphase Circuits 47 Three-Phase Loads 5 Important Circuit and System Concepts 51 Frequency Response 52 Resonance 53 Complex Frequency 54 Introduction to Systems 55 The Laplace Transform 56 Inverse Laplace Transforms 57 Application of the Laplace Transform PART II: ELECTRONICS 6 Diodes 61 Semiconductors 62 Doped Semiconductors 63 The Junction Diode 64 The Ideal Diode 65 Nonideal-Diode Models 66 Zener Diodes 67 Effects of Capacitance 7 Bipolar Junction Transistors (BJTs) 7,1 The pnp Transistor 72 The npn Transistor 73 Cutoff and Saturation 74 Applications to Digitial Logic Circuits 75 DTL Integrated-Circuit (IC) Logic 76 Transistor-Transistor Logic (TTL) 77 Other IC Logic Families 8 Field-Effect Transistors (FETs) 81 The Junction Field-Effect Transistor (JFET) 82 Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) 83 MOSFET Logic Gates 8,4 Complementary MOSFETs (CMOS) 9 Transistor Amplifiers 91 BJT Amplifiers 92 FET Amplifiers 93 Frequency Response 94 Power Amplifiers 10 Electronic Circuits and Amplifiers 101 IC Amplifiers 102 Operational Amplifiers 103 Feedback 104 Sinusoidal Oscillators 105 Comparators 106 Introduction to Communication PART III: DIGITAL SYSTEMS 11 Digital Logic 111 Binary Numbers 112 Binary Arithmetic 113 Digital Logic Circuits 114 Boolean Algebra 115 Standard Forms of Boolean Functions 116 Simplification of Boolean Functions 12 Logic Design 121 Combinatorial Logic 122 MSI and LSI Design 123 Sequential Logic 13 Digital Devices 131 Counters 132 Registers 133 Memories 134 Digital Information Processing PART IV: ELECTROMAGNETICS 14 Electromagnetics 141 Magnetic Fields 142 Magnetic Circuits 143 Transformers 144 The Ideal Tranformer 145 Nonideal-Transformer Models 15 Machines 151 Tranducers 152 Moving-Coil and Moving-Iron Devices 153 Rotating-Coil Devices 154 Generators 155 Motors PART V: SPICE 16 SPICE 161 PSPICE 162 Transient Analysis 163 AC Analysis 164 Diodes 165 Dipolar Junction Transistors (BJTs) 166 Field-Effect Transistors (FETs) 167 Transistor Amplifiers 168 Operational Amplifiers

Logic analysis system for logic emulation systems

Abstract: A portion of a logic emulation system is configured to sample logic values from the portion of the emulation system that is used to emulate the user digital logic design. These sampled values are then multiplexed by the emulation system to a logic analysis device. Typically, this is a commercially-available logic analyzer. To achieve this functionality, the emulation system is provided with a clock signal that has a higher frequency than the emulation clock signal received from the target or user system. This high speed clock signal is provided to logic analyzer as a strobe signal and controls the transfer of words of logic values from the emulation system to the logic analyzer. As a result, the number of signals that the logic analyzer can effectively sample for a cycle of the emulation clock is increased. Each probe of the logic analyzer can now receive multiple time-division multiplex logic values for each emulation clock cycle thus, increasing the width of logic analysis that can be performed on a particular emulation system with the conventional logic analyzers.

Exploiting multicycle false paths in the performance optimization of sequential logic circuits

Abstract: This paper addresses the performance optimization problem for sequential logic circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. These multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. An implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a modest area overhead. >

Low-power CMOS threshold-logic gate

Abstract: A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design.

IDDQ testing of CMOS opens: an experimental study

Abstract: IDDQ testing is known to be very effective in detecting shorts in CMOS circuits. It has also been reported that open defects that lead to "floating" transistor gates can also be detected if the gate acquires a sufficient voltage to leak measurable current. Recent experiments evaluating a new on-chip IDDQ sensor indicated the possibility of additional detection mechanisms for other types of open failures, including open source and drain connections. To investigate this in more detail, we designed and fabricated two test chips in CMOS technology containing the 74181 ALU circuit. Our test chips include the capability of replacing, one at a time, individual cells in the 74181 circuits with back up cells that each contain a single open defect. In this way in addition to the fault free circuits, a total of 59 faulty circuits can be configured, each containing a different open defect. It was found that IDDQ testing with random vectors detected 48 of the 59 open defects. Analysis of the experimental data reveals new mechanisms that explain the detection of floating gate and open source and drain failures.

Regenerative feedback repeaters for programmable interconnections

Abstract: FPGA performance is limited mainly by the delay of the programmable interconnection network. This delay increases quadratically with the number of series switches, and is a problem especially when the programmable switches are implemented using MOS transistors, since these have an appreciable resistance and capacitance. The delay can be reduced, at the cost of routability, by limiting the number of series switches per interconnection, or at the cost of area by inserting repeaters. Conventional bidirectional repeaters consist of sets of unidirectional tristate buffers and memory cells. Their benefit is limited due to high area and delay penalty. Area and delay penalty can be alleviated by using a regenerative feedback that senses the beginning of a transition and subsequently enforces it. This requires one buffer and no memory cells. This article shows a network with such repeaters for direction-independent buffering.

Tileable gate array cell for programmable logic devices and gate array having tiled gate array cells

Abstract: A logic and routing cell for constructing a programmable gate array. The gate array may be constructed by tiling a wafer surface with this single logic and routing cell design. The logic and routing cell includes both the logic cell and the routing circuitry needed to connect that logic cell to all levels of a hierarchical routing system for making connections between the various logic cells.

Clocked CMOS Adiabatic Logic with Single AC Power Supply

Abstract: This paper describes a low-power clocked CMOS adiabatic logic (CAL) with only one ac power supply that serves as the power clock. Each CAL stage performs true and complementary logic functions, and presents a constant capacitive load to the power clock generator. A simple and efficient resonant power clock is integrated with the logic to generate the required ac supply waveform and facilitate adiabatic energy transfers. Energy savings comparable to adiabatic logic families that require multi-phase power clocks have been verified by simulation tests of the CAL supplied by the integrated power clock generator.

Leading-zero anticipatory logic for high-speed floating point addition

Abstract: This paper describes new Leading-Zero Anticipatory (LZA) Logic for high-speed floating-point addition (FADD). This method carries out the pre-decoding for the normalization concurrently with the addition for significand. Besides, it performs the shift operation in parallel with the rounding operation. The proposed logic consists of the simple circuit with 1.8% penalty in transistor count. The FADD core using the proposed logic operates at 160 MHz, where the core has been fabricated with 0.5 /spl mu/m CMOS technology with triple metal interconnections.

A comparative study of switching activity reduction techniques for design of low-power multipliers

Abstract: The design of portable battery-operated systems requires multiplication circuits of low switching activity. This paper studies multiplication algorithms, sign extension methods, adding structures, resource sharing and component schematic alternatives from the point of decreasing the total number of logic transitions in the target multiplication circuit. Experiments show, that by utilizing the signed-digit encoding scheme, modified sign extension technique, 4-2 adding compressors and swing restored transistor path logic, a twice as low switching activity can be achieved.

The Validity of Retiming Sequential Circuits

Abstract: Retiming has been proposed as an optimization step for sequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so changes the number of latches and the longest path delay between the latches. In this paper we show by example that retiming a design may lead to differing simulation results when the retimed design replaces the original design. We also show, by example, that retiming may not preserve the testability of a sequential test sequence for a given stuck-at fault as measured by a simulator. We identify the cause of the problemas forward retiming moves across multiple-fanout points in the circuit. The primary contribution of this paper is to show that, while an accurate logic simulation may distinguish the retimed circuit fromthe original circuit, a conservative three-valued simulator cannot do so. Hence, retiming is a safe operation when used in a design methodology based on conservative three-valued simulation starting each latch with the unknown value.

LOT: logic optimization with testability—new transformations using recursive learning

Abstract: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates derived based on indirect implications by Recursive Learning have been introduced in the synthesis of multi-level circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology can not only realize lower area, but also achieves better testability compared to testability enhancement synthesis tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations can yield smaller circuits compared to state-of-the-art logic optimization tools like SIS and HANNIBAL.

Data output buffer using pass transistors biased with a reference voltage and a precharged data input

Abstract: A data output buffer circuit for a semiconductor device for transferring read cell data to the peripheral circuits, comprising an input terminal for inputting the read cell data, a first NMOS transistor for transferring the data from the input terminal when it has a first logic level, a first PMOS transistor for transferring the data from the input terminal when it has a second logic level, a second PMOS transistor for transferring a high logic signal in response to an output signal from the first NMOS transistor, a second NMOS transistor for transferring a low logic signal in response to an output signal from the first PMOS transistor, and an output terminal for outputting the high logic signal from the second PMOS transistor or the low logic signal from the second NMOS transistor to the peripheral circuits.