Showing papers on "Pass transistor logic published in 1998"

Digital circuit applications of resonant tunneling devices

Abstract: Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's) New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates

Emulation system with time-multiplexed interconnect

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into th e programmable resources in the logic chips of the emulation system.

CMOS circuit design of threshold gates with hysteresis

Abstract: M-of-N threshold gates with hysteresis form a class of circuit elements that have important application in NULL Convention Logic/sup TM/, a novel asynchronous logic design methodology. General design guidelines for these M-of-N gates are presented using CMOS technology. Three types of circuit implementations are discussed: static, semi-static and dynamic. In addition, initialization techniques are presented for use in establishing a known initial state.

High-speed and low-power operation of a resonant tunneling logic gate MOBILE

Abstract: High-speed operations up to 35 Gb/s were demonstrated for a resonant tunneling (RT) logic gate monostable-bistable transition logic element (MOBILE). The test circuit consisted of a MOBILE and a DCFL-type output buffer, and it was fabricated using InP-based resonant tunneling diode/HEMT integration technology. This operation bit rate is close to the cutoff frequency of the 0.7-/spl mu/m gate HEMTs used in the circuit, and was obtained after improvement of the output buffer design. This result indicates the high-speed potential of the MOBILE, though the speed is still limited by the buffer. The power dissipation of the MOBILE was also discussed based on a simple equivalent circuit model of RTDs. This revealed that the power dissipation is as small as 2 mW/gate over a wide range of operation bit rates.

High density and high speed magneto-electronic logic family

Abstract: A number of novel new devices and circuits are disclosed utilizing configurable magneto-electronic elements such as magnetic spin transistors and hybrid hall effect devices. Such magneto-electronic elements can be used as building blocks of an entirely new family of electronic devices for performing functions not easily implementable with semiconductor based device. A number of examples are provided, including logic gates that can be programmed to perform different boolean logic operations at different periods of time. Logic devices and circuits incorporating such logic gates have a number of operational advantages and benefits over conventional semiconductor based technologies, including the fact that traditional signal logic operations can be implemented with substantially fewer active elements. A conventional boolean function unit, for example, can be constructed with 2 magneto-electronic elements, and 2 semiconductor elements, which is a 400% improvement over prior art pure semiconductor based technologies.

Programmable function block

Abstract: A programmable function block 20 comprises a logic block 21 including a full adder 31 and at least one preposition logic 32, and an input block 22 including programmable input switch units 40-1 through 40-9 for use in selectively switching a HIGH logic level signal, a LOW logic level signal, and a signal on interconnection lines 50. The preposition logic 32 comprises an exclusive OR circuit 32-1 and a multiplexer 32-2 and functions as various different logic circuits by means of setting some of the inputs thereof to a HIGH logic level or a LOW logic level. Thus, the logic block functions as various different logic circuits depending on the state of the inputs. In addition, the full adder provides fast arithmetic operation.

Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output

Abstract: By using resonant-tunneling diodes (RTDs) and high electron mobility transistors (HEMTs), we implement a new class of logic circuits that operate with multiple thresholds and multilevel output. The basic idea of the circuits is to synthesize transfer characteristics by key logic elements, namely, up and down literals. We first describe two fundamental logic circuits based on this idea: a ternary inverter and a literal gate. Then we present experimental results on these circuits fabricated by integrating InP-based RTDs and HEMTs. It is found that these circuits operate successfully with threshold voltages and output levels that have been predicted from individual device characteristics. Consequently, the validity of the basic idea behind the circuits presented here is proven. The device counts and the number of logic stages required for the present circuits are less than half those for conventional ones. A possible application is finally discussed.

Redundancy circuitry for programmable logic devices with interleaved input circuits

Abstract: Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.

MOS logic circuit and semiconductor apparatus including the same

Abstract: A MOS logic circuit includes: a pass-transistor logic circuit, including at least one first MOS transistor, for performing a predetermined logic operation to provide an output; and an amplifying circuit, including at least one second MOS transistor, for enhancing a driving capability of the output of the pass-transistor logic circuit. Each of the first MOS transistor and the second MOS transistor is a DTMOS transistor having a gate connected to an associated well in which a channel thereof is formed.

A new design of double edge triggered flip-flops

Abstract: The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 /spl mu/ technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time, and higher maximum data rate compared to other existing CMOS DET flip-flops. By simulating and comparing the proposed DET flip-flop with the traditional single-edge-triggered (SET) flip-flop, it is shown that the proposed DET flip-flop reduces power dissipation by half while keeping the same date rate.

Issue logic for a 600-MHz out-of-order execution microprocessor

Abstract: The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.

Pass-transistor adiabatic logic with NMOS pull-down configuration

Abstract: A new low power adiabatic logic family, pass-transistor adiabatic logic with NMOS pull-down configuration, is presented. For a 2:1 multiplexer, a power saving of ~80% is achieved, compared to a 2N-2N2P logic circuit at 20 MHz. Compared to pass-transistor adiabatic logic using single power-clock supply (PAL), the ‘tri-state’ problem is solved, while power consumption is comparable. A four phase sinusoidal clock power supply is employed in the new logic family, which facilitates pipelining hence leading to higher throughput, compared to PAL.

Programmable logic device having combinational logic at inputs to logic elements within logic array blocks

Abstract: AND gates are used at the inputs to logic elements in a programmable logic device. This allows more efficient configuration of the logic elements for basic functions such as a multiplier, clearable counter and multiplexer. Inputs to the AND gates are enabled by LAB-wide control signals that are distributed to several logic elements within a logic array block. The control signals can also be generated from a RAM or ROM, or by decoding existing control signals.

Programmable logic device circuitry for improving multiplier speed and/or efficiency

Abstract: In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.

Low voltage, low power static random access memory cell

Abstract: A ten transistor low voltage, low power static random access memory cell (10) includes a first inverter (12) cross-coupled to a second inverter (18). A series combination of a first pass transistor (24) and a first bitline select transistor (28) is connected between an output node (13) of the first inverter (12) and a first bitline (36). A first write pass transistor (32) is placed in parallel with the first pass transistor (24). A series combination of a second pass transistor (26) and a second bitline select transistor (30) is connected between an output node (17) of the second inverter (18) and a second bitline (38). A second write pass transistor (34) is placed in parallel with the second pass transistor (26).

Reconfigurable multiplier array

Abstract: This invention provides a logic block comprising an mxn array of partial calculating circuits (where m≧2 and n≧2) operable to generate partial product components of an m-bit multiplicand x n-bit multiplicand binary multiplication and to generate a cumulative sum of the partial products for each bit of one of the multiplicands. A configurable output circuit which is operable under the control of a configuration signal either (a) to sum the cumulative sums of partial products generated by the partial calculating circuits so as to generate a product value, or (b) to pass data representing the cumulative sums of the partial product components to partial calculating circuits within one or more further logic blocks. Also provided is a logic circuit including two or more such logic blocks, data interconnections for data transfer between the logic blocks and control interconnections for control signal transfer to the logic blocks.

Power control apparatus and method for a body implantable medical device

Abstract: An apparatus and method for controlling power in digital logic circuitry is disposed in a body implantable biomedical device disclosed. A power switch, such as a power gating transistor, is coupled to a digital logic circuit element to selectively control the application of power to the circuit element. During each system clock cycle, power is supplied to the circuit element only for a duration of time required to effect switching of logic states. Power is removed from the circuit element during each system clock cycle when no switching of logic states occurs. A clock signal applied to the gate of a power gating transistor selectively controls the supply of power to the digital circuit logic element during each system clock cycle so as to appreciably reduce static power consumption of the circuit element. The power control apparatus and method may be implemented in any digital logic design, and is well suited for use in digital circuitry that employs combinatorial logic of any complexity and any number of registers or latches. The appreciable reduction in static power consumption realized by employing the power control apparatus and method according to the present invention is particularly useful in digital logic circuitry applications designed to operate at relatively low switching frequencies and low power, such as implantable biomedical device applications.

Fuzzy logic control of a space-vector PWM current regulator for three-phase power converters

Abstract: This paper presents a fuzzy logic implementation of space-vector pulse-width modulation (PWM) for three-phase power converters. The conventional space-vector PWM current regulator implementation is generally computationally complex. The fuzzy logic controller implementation relieves the processor of a number of computations, thereby accommodating a less expensive microprocessor. The AC-side rectifier voltages are used as fuzzy-state variables. The fuzzy logic control has two outputs: magnitude and angle of reference voltage. Both conventional space-vector PWM and the fuzzy logic controller are implemented to evaluate performance using a 16-b microcontroller (68HC16). Experimental results are provided for both controllers at the same operating point, where the power drawn by the load is about 3 kW. The fuzzy logic controller reduces the computational burden on the processor by about 30%.

Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits

Abstract: This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods.

Breaking the 2n-bit carry propagation barrier in residue to binary conversion for the [2/sup n/-1, 2/sup n/, 2/sup n/+1] modula set

Abstract: This work presents a high speed realization of a residue to binary converter for the (2/sup n/-1, 2/sup n/, 2/sup n/+1), moduli set, which improves upon the best known implementation by almost twice in terms of overall conversion delay. This significant speedup is achieved by using just three extra two input logic gates. Interestingly, by exploiting certain symmetry in operands, we also reduce the hardware requirement of the best known implementation by n-1 full adders. Finally, the proposed converter eliminates the redundant representation of zero using no extra logic.

Clock-controlled neuron-MOS logic gates

Abstract: A new clock-controlled circuit scheme has been introduced in the basic architecture of neuron-MOS (neuMOS or /spl nu/MOS) logic gates. In this scheme, the charge on a neuMOS floating gate is periodically refreshed by a clock-controlled switch. A special refreshing scheme in which fluctuations in device parameters are automatically canceled has been employed. As a result, the number of multiple logic levels that can be handled in a neuMOS floating gate has been increased. In addition, the data subtraction operation directly conducted on the floating gate has become possible. All of these circuit techniques have enhanced the functionality of a neuMOS logic gate a great deal. In order to achieve a low power operation, latched-sense-amplifier circuitries are also introduced for logic decision. Test circuits were fabricated in a double-polysilicon CMOS process, and the basic circuit operations are demonstrated.

Logic element for a programmable logic integrated circuit

Abstract: A logic element (300) for a programmable logic device. The logic element (300) allows two independent logic functions to be carried out during the same clock cycle. A 4-input look-up table (406) is provided using a 3-input look-up table (434) and two 2-input look-up tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic device.

Single-electron-parametron-based logic devices

Abstract: We analyze the operation of the wireless single-electron logic family based on single-electron-parametron cells. Parameter margins, energy dissipation, and the error probability are calculated using the orthodox theory of single-electron tunneling. Circuits of this family enable quasireversible computation with energy dissipation per bit much lower than the thermal energy, and hence may circumvent one of the main obstacles faced by ultradense three-dimensional integrated digital circuits.

Technology mapping for large complex PLDs

Abstract: In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consists of a large number of PLA-style logic blocks. Although the traditional synthesis approach for such devices uses two-level minimization, the complexity of recently-produced CPLDs has resulted in a trend toward multi-level synthesis. We describe an approach that allows existing multi-level synthesis techniques [13] to be adapted to produce circuits that are well-suited for implementation in CPLDs. Our algorithm produces circuits that require up to 90% fewer logic blocks than the circuits produced by a recently-published algorithm.

Multiple-junction single-electron transistors for digital applications

Abstract: The concept of the capacitively coupled single-electron transistor (CSET) is generalized to a device based on a linear array of N tunnel junctions. The basic characteristics of such multiple-junction CSETs are calculated for several distributions of tunnel junction and coupling capacitances. The results indicate that for optimized parameters, the operating temperature and parameter tolerances increase appreciably with N, with the most striking gains for N≲5. For example, a five-junction transistor may provide a 2.5-fold increase of the maximum operating temperature, for the same minimum feature size.

Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program

Abstract: Information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit are inputted through circuit information I/O portion. Enable logic timing constraint generating portion generates timing constraint to be secured for enable logic. Enable logic timing determination portion calculates a delay time in the enable logic and determines whether or not the enable logic satisfies the timing constraint based on the delay time. Clock gating execution portion, when the enable logic satisfies the timing constraint, adds a gating circuit and a circuit composed of the enable logic to a logic circuit not clock-gated so as to generate a clock-gated logic circuit. Circuit information I/O portion outputs information about the clock-gated logic circuit and timing constraint to be secured for the enable logic.

Method and structure for dynamic in-system programming

Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

RAM-based FPGA's: a test approach for the configurable logic

Abstract: This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of test configurations 8 is fixed and independent of the FPGA size.

Family of logic circuits emploting mosfets of differing thershold voltages

Abstract: This invention involves logic circuits formed of metal oxide semiconductor field effect transistors having differing threshold voltages. In a first embodiment, the logic circuit includes a first and a second series connection. The first series connection between a first supply voltage and an output node consists of a source-drain path of an N-channel transistor having a high threshold voltage and a pull-down conditional conduction path of a pull-down network constructed exclusively of transistors having a low threshold voltage. The second series connection between said supply voltage and said output node consists of a source-drain path of a P-channel transistor having the high threshold voltage and a pull-up conditional conduction path of a pull-up network constructed exclusively of transistors having the low threshold voltage. The two high threshold voltage MOSFETs receive at their respective gates inverse signals so that either both are conducting or both are off. The pull-down network and pull-up network each receives input signals which control whether they conduct. These input signals are preferably selected so that the pull-down network and pull-up network do not conduct simultaneously. The two parts of each series connection may be in either order. The first input signal is preferably a clock signal. The pull-down network is preferably constructed exclusively of N-channel transistors. The pull-up network is preferably constructed exclusively of P-channel transistors.