Showing papers on "Pass transistor logic published in 1999"

Electronically Configurable Molecular-Based Logic Gates

Abstract: Logic gates were fabricated from an array of configurable switches, each consisting of a monolayer of redox-active rotaxanes sandwiched between metal electrodes. The switches were read by monitoring current flow at reducing voltages. In the “closed” state, current flow was dominated by resonant tunneling through the electronic states of the molecules. The switches were irreversibly opened by applying an oxidizing voltage across the device. Several devices were configured together to produce AND and OR logic gates. The high and low current levels of those gates were separated by factors of 15 and 30, respectively, which is a significant enhancement over that expected for wired-logic gates.

Digital logic gate using quantum-Dot cellular automata

Abstract: A functioning logic gate based on quantum-dot cellular automata is presented, where digital data are encoded in the positions of only two electrons. The logic gate consists of a cell, composed of four dots connected in a ring by tunnel junctions, and two single-dot electrometers. The device is operated by applying inputs to the gates of the cell. The logic AND and OR operations are verified using the electrometer outputs. Theoretical simulations of the logic gate output characteristics are in excellent agreement with experiment.

A new RTD-FET logic family

Abstract: We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules.

Ultra-low power digital subthreshold logic circuits

Abstract: Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region.

FPGA routing architecture: segmentation and buffering to optimize speed and density

Abstract: In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transistor and tri-state buffer routing switches. While most commercial FPGAs contain many length 1 wires (wires that span only one logic block) we find that wires this short lead to FPGAs that are inferior in terms of both delay and routing area. Our results show instead that it is best for FPGA routing segments to have lengths of 4 to 8 logic blocks. We also show that 50% to 80% of the routing switches in an FPGA should be pass transistors, with the remainder being tri-state buffers. Architectures that employ the best segmentation distributions and the best mixes of pass transistor and tri-state buffer switches found in this paper are not only 11% to 18% faster than a routing architecture very similar to that of the Xilinx XC4000X but also considerably simpler. These results are obtained using an architecture investigation infrastructure that contains a fully timing-driven router and detailed area and delay models.

A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors

Abstract: In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main features of the basic design are short latency, small clock load, small area, and a single-phase clock scheme. Furthermore, the flip-flop family has the capability of easily incorporating logic functions with a small delay penalty. This feature greatly reduces the pipeline overhead, since each flip-flop can be viewed as a special logic gate that serves as a synchronization element as well.

Digital Integrated Circuit Design

Abstract: Preface 1. THE BASICS 1.1 Simple NMOS Logic Gates 1.2 Simple CMOS Logic Gates 1.3 Computer Simulation 1.4 Transfer Curves and Noise Margins 1.5 Gate Delays and Rise and Fall Times 1.6 Transient Response 1.7 An RC Approximation to the Transient Response of a CMOS Inverter 1.8 Summary 1.9 Bibliography 1.10 Problems 2. PROCESSING, LAYOUT, AND RELATED ISSUES 2.1 CMOS Processing 2.2 Bipolar Processing 2.3 CMOS Layout and Design Rules 2.4 Advanced CMOS Processing 2.5 Bibliography 2.6 Problems 3. INTEGRATED-CIRCUIT DEVICES AND MODELING 3.1 Simplified Transistor Modeling 3.2 Semiconductors and pn Junctions 3.3 MOS Transistors 3.4 Advanced MOS Modeling 3.5 Bipolar-Junction Transistors 3.6 SPICE-Modeling Parameters 3.7 Appendix 3.8 SPICE Simulations 4. TRADITIONAL MOS DESIGN 4.1 Pseudo-NMOS Logic 4.2 Pseudo-NMOS Logic Gates 4.3 Transistor Equivalency 4.4 CMOS Logic 4.5 CMOS Gate Design 4.6 SPICE Simulations 4.7 Bibliography 4.8 Problems 5. TRANSMISSION-GATE AND FULLY DIFFERENTIAL CMOS LOGIC 5.1 Transmission-Gate Logic Design 5.2 Differential CMOS Circuits 5.3 Bibliography 5.4 Problems 6. CMOS TIMING AND I/O CONSIDERATIONS 6.1 Delay of MOS Circuits 6.2 Input/Output Circuits 6.3 Bibliography 6.4 Problems 7. LATCHES, FLIP-FLOPS, AND SYNCHRONOUS SYSTEM DESIGN 7.1 CMOS Clocked Latches 7.2 Flip-flops 7.3 CMOS Flip-flops 7.4 Synchronous System Design Techniques 7.5 Synchronous System Examples 7.6 Bibliography 7.7 Problems 8. BIPOLAR AND BICMOS LOGIC GATES 8.1 Emitted-Coupled Logic Gates 8.2 Current-Mode Logic 8.3 BiCMOS 8.4 SPICE Simulations 8.5 Bibliography 8.6 Problems 9. ADVANCED CMOS LOGIC DESIGN 9.1 Pseudo-NMOS and Dynamic Precharging 9.2 Domino-CMOS Logic 9.3 No-Race-Logic 9.4 Single-Phase Dynamic Logic 9.5 Differential CMOS 9.6 Dynamic Differential Logic 9.7 Bibliography 9.8 Problems 10. DIGITAL INTEGRATED SYSTEM BUILDING BLOCKS 10.1 Multiplexors and Decoders 10.2 Barrel Shifters 10.3 Counters 10.4 Digital Adders 10.5 Digital Multipliers 10.6 Programmable Logic Arrays 10.7 Bibliography 10.8 Problems 11. INTEGRATED MEMORIES 11.1 Static Random-Access Memories 11.2 Static Random-Access Memory Storage Cells 11.3 Address Buffers and Decoders 11.4 Dynamic Bus Precharge and Address-Transition-Detect Circuits 11.5 Modifications for Large Static Random-Access Memories 11.6 Dynamic Random-Access Memories 11.7 Read-Only Memories 11.8 Bibliography 11.9 Problems 12. GAAS DIGITAL CIRCUITS 12.1 Introduction 12.2 GaAs Processing and Components 12.3 MESFET Modeling 12.4 MESFET Second-Order Effects 12.5 Logic Design with MESFETs 12.6 Capacitively Enhanced Logic 12.7 GaAs Logic Family Comparison 12.8 Heterojunction Bipolar Technology 12.9 Bibliography 12.10 Problems 13. DIGITAL SYSTEM TESTING 13.1 Conservative Design Principles 13.2 Scan-Design Techniques 13.3 Localized Test-Vector Generation and Test-Output Compression Techniques 13.4 Boundary-Scan Testing 13.5 Bibliography 13.6 Problems

Bit line control circuit for a memory array using 2-bit non-volatile memory cells

Abstract: A bit line control circuit for accessing an array of 2-bit non-volatile memory cells. Each memory cell has a first and a second charge trapping regions. A set of bit lines extends between the array and the bit line control circuit. The bit line control circuit includes pass transistors that selectively route pairs of bit lines to corresponding voltage control circuits in either a first order or a second (reversed) order. This enables both the first and second charge trapping regions of the memory cells to be accessed from the same voltage control circuits. In one embodiment, the bit line control circuit includes a first-level pass transistor coupled to each bit line. A second set of bit lines is coupled to the first-level pass transistors. A parallel-connected pair of second-level pass transistors is coupled to each bit line in the second set of bit lines. A third set of bit lines is coupled to the second-level pass transistors. The voltage control circuits are coupled to the third set of bit lines. The voltage control circuits apply voltages to the third set of bit lines to perform read, write and erase operations in the memory cells of the memory array. The first and second level pass transistors provide a consistent path for accessing all memory cells in the array, as well as handling the edge conditions introduced by the right-most and left-most columns of memory cells.

A comprehensive delay macro modeling for submicrometer CMOS logics

Abstract: The increasing need for high-performance, cost-effective, application-specific integrated circuits, associated to the reduction of design cycle time, compels designers to manage and optimize the circuit speed performance at each step of the design flow. Circuits are usually designed at gate level; the gate selection or sizing and their placement are driven by estimated delay, hence the need for accurate estimations at the logical level. In the submicrometer range, the gap between gate-level logical estimations and transistor-level electrical simulations dramatically increases. We propose here a comprehensive analytical modeling of the speed performance of CMOS gates with an accuracy comparable to electrical simulators. A design-oriented expression of delay is first developed for CMOS inverters, considering input slope, input-to-output capacitance coupling, and short-circuit current effects. The extension to more complex gates is proposed using a serial array reduction technique taking account of the gate input dependency and the input-slope-induced nonlinearity. Validations are obtained over a large range of design, load, and input slope conditions by comparison with SPICE simulations (level 6 with 0.65-/spl mu/m foundry specified card model) used as a reference.

Power-on-reset logic with secure power down capability

Abstract: Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

Soft error considerations for deep-submicron CMOS circuit applications

Abstract: The increasing importance of characterizing both memory arrays and core logic when estimating soft error FIT (failure in time) rates has been demonstrated using test-circuits, a 21264 Alpha microprocessor, and simulations. The reduction of operating voltage has been determined to increase the soft error rate exponentially at 2.1-2.2 decades/volt. Based on the SIA roadmap for CMOS scaling trends, meeting FIT rate requirements in the core logic will pose many challenges in the imminent future.

Partially-depleted SOI technology for digital logic

Abstract: This partially-depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology. A number of SOI-unique effects that complicate device and circuit design are discussed, along with possible remedies. A fully functional 32 bit microprocessor, operating at >500 MHz, demonstrates this SOI technology.

Overview of low-power ULSI circuit techniques

Abstract: This chapter contains sections titled: Minimizing Power Consumption in Digital CMOS Circuits Overview of Low-Power ULSI Circuit Techniques Multi-Level Pass-Transistor Logic for Low-Power ULSIs High Performance, Energy Efficient Master-Slave Flip-Flop Circuits Power Dissipation in the Clock System of highly pipelined ULSI CMOS Circuits Power-Delay Characteristics of CMOS Adders Delay Balanced Multipliers for Low Power/Low Voltage DSP Core Minimization of Power in VLSI Circuits Using Transistor Sizing, Input Ordering, and Statistical Power Estimation Low-Power Digital Design Power Analysis of a Programmable DSP for Architecture/Program Optimization A Review of Adiabatic Computing 2ND Order Adiabatic Computation with 2N-2P and 2N-2N2P Logic Circuits A Low-Power Microprocessor Based on Resonant Energy Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply: Experimental Results

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

Abstract: We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

Electronics - Circuits and Systems

Abstract: Essential facts: useful terms and equations useful circuits circuit calculations. Devices: diodes transistors sensors and transducers. Circuits: amplifiers oscillators operational amplifiers more operational amplifier applications power amplifiers power control devices logic circuits combinatorial logic sequential logic display devices conversion devices. Communication systems: communication transmission media noise signals radio communication. Systems: control systems microprocessor systems microprocessors memory programming software. Fault-finding: inspecting for faults faults in analogue circuits faults in digital circuits.

Semiconductor logic circuit device of low current consumption

Abstract: A logical processing part is formed by a pass transistor logic element, and an output signal of the pass transistor logic element is applied to the gates of MOS transistors for differentially amplifying and latching the output signal in the latch stage. This latch stage is formed by master and slave latch circuits, and power supply to the master latch circuit is cut off while holding an information signal only in the slave latch circuit with the level of a power supply voltage thereto increased, reducing a leakage current in a sleep mode or a power down mode. A logic circuit correctly operating at a high speed with low current consumption under a low power supply voltage is provided.

Context switchable field programmable gate array with public-private addressable sharing of intermediate data

Abstract: A context switching logic cell with public and context private data sharing for use in a context switching system. A context switching logic cell includes a programmable logic unit using configuration bits for implementing programmable logic functions for each context, a context memory for storing and providing results of context dependent logic operations, and carry logic. The context memory includes private registers, public registers and an active register. Each private register corresponds to a context and is addressable only within the corresponding context while public registers are addressable within all contexts and the active register stores results of logic operations for the current context. A context switching logic cell may include a data memory that is accessible within all contexts. The context switching logic cells may be arranged into a context switching logic array for use in a context switching system by level 1 buses and carry bit lines. Logic arrays may be interconnected into pipelines by level 2 buses and bidirectional paths connecting sequentially adjacent logic array. A plurality of pipelines may be interconnected in parallel into a context switching system by a third level bus interconnecting the second level buses of the pipelines and carry lines between the corresponding context switching logic arrays of adjacent context switching pipelines.

Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks

Abstract: A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.

100 nm gate length high performance/low power CMOS transistor structure

Abstract: We report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V. These transistors are incorporated in a 180 nm logic technology generation. Various process enhancements are incorporated to significantly improve transistor current drive capability relative to the results published by Yang et al. (1998). Unique transistor features responsible for achieving high performance are described. NMOS and PMOS devices demonstrate drive current of 1.04 mA//spl mu/m and 0.46 mA//spl mu/m respectively at 1.5 V and 3 nA//spl mu/m I/sub OFF/. These are the best drive currents reported to date at fixed I/sub OFF/. They represents 10% drive current improvement for both NMOS and PMOS devices relative to the results published by Yang without any change in gate-oxide thickness. High performance is demonstrated down to 1.2 V. Inverter delay of less than 10 psec is reported at 1.5 V at very moderate I/sub OFF/ values.

Single event transients in deep submicron CMOS

Abstract: Single event transients (SET) occur when an energetic subatomic particle strikes a combinational logic element. The charge deposited by the particle causes a transient voltage disturbance, which can propagate to a storage element and be latched, resulting in single event upset (SEU). The logic design style, storage element behavior, and system timing requirements greatly impact the probability that an SET will cause an SEU. These effects are explored through circuit simulations and heavy ion testing of prototype devices.

Programmable logic integrated circuit architecture incorporating a global shareable expander

Abstract: A logic element for a programmable logic device to implement a global shareable expander. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

Dual threshold voltage domino logic

Abstract: Dual threshold voltage (DVT) domino logic utilizes dual V t 's to provide the performance equivalent of a purely low V t design with the standby leakage characteristic of a purely high V t implementation. DVT domino logic is an attractive circuit style compared to other dual V t techniques because there are no performance penalties, no difficult transistor sizing issues, and all gates (not just non-critical ones) can be compensated. In fact, any low V t domino design can easily be converted to a dual V t implementation with superior characteristics.

System and method for reducing power dissipation in a circuit

Abstract: A system for the selective allocation of power to elements of an integrated circuit. A logic component (12) identifies at least one element (36) of the integrated circuit for reduced power dissipation and selects this element by a selection signal. A control interface (38) reduces the power dissipated by the selected element. This may be achieved by: selecting one of two power supplies having the lower voltage; reducing a clock frequency; modifying a threshold voltage of a transistor in the element in response via a voltage regulator; selecting one of two devices in parallel connected to a lower power supply voltage. The logic component may be a an instruction handler (30) which identifies whether an instruction uses the element or which processes a power down instruction the element. The element may an arithmetic logic unit, an adder, a register or a transistor.

Circuit design, transistor sizing and wire layout of FPGA interconnect

Abstract: This paper examines the electrical design of FPGA interconnect circuitry. We explore the circuit design of pass transistor and tri-state buffer routing switches, determine which transistor sizing, metal width and metal spacing are best for FPGA interconnect, and show that FPGA interconnect should be electrically heterogeneous-some (/spl sim/20%) of the routing tracks should be designed for maximum speed while the remainder should be more area-efficient.

A 10-transistor low-power high-speed full adder cell

Abstract: In this paper, we introduce a high-speed low-power 10-transistor 1-bit full adder cell. The critical path consists of an XOR gate; an inverter and one pass transistor. A prototype of the proposed adder cell in 0.6 /spl mu/m CMOS technology has an average delay time of 0.084 ns. It also exhibits low average power dissipation of 0.891/spl times/10/sup -4/ watt at frequency equal to one GHz. In an n-bit adder circuit, the new adder cell will give alternate polarity for the carryout in the odd and even positions. The inverters in the structure of the proposed FA cell act as drivers. Therefore, each stage will not suffer a degradation in its deriving capabilities. This saves power, area, and time. The new cell is used to build a prototype for a 32-bit ripple carry adder. This prototype has 384 transistors and it operates at 2.8 V with an average delay of 4.1 ns, and a low power dissipation of 2.6 mW at frequency equal to 250 MHz.

Integrated circuit with standard cell logic and spare gates

Abstract: An integrated circuit comprises an array of standard cell logic having spare gate logic dispersed therein. The spare gate logic is connectable to the standard cell logic through upper level conductors. This allows the design of an integrated circuit to be changed by changing the pattern of the upper level conductors, thereby lowering the cost of making a design change and reducing the disturbance of the original wiring. In an illustrative embodiment, the top two or three metal levels and associated vias are mask-programmable for this purpose. The interconnections from the mask-programmable upper levels to the underlying standard cell logic is accomplished using a regular array of conductor vias interspersed throughout the standard cell array, plus elevated output terminal which create a loop structure completed by the program levels. This allows output terminal loops of the standard cells to be brought up to the mask-programmable metal levels for removal of any standard cell logic. The spare gate logic comprises a relatively small percentage of logic gates as compared to the standard cell logic (typically less than 20 percent). This allows for the economies of production usually associated with conventional standard-cell ASIC arrays, while providing for economical and rapid repair of logic errors and/or the implementation of changes in logic functionality, by requiring changes in only the top metal levels.

Multiple-valued logic circuit architecture: supplementary symmetrical logic circuit structure (sus-loc)

Abstract: Circuit structure and resulting circuitry for multiple-valued logic. The circuit structure allows the design and fabrication of any r-valued logic function of n-places where r is an integer greater than 1 and n is an integer greater than 0. This structure is called SUpplementary Symmetrical LOgic Circuit structure (SUS-LOC). In circuits incorporating SUS-LOC, circuit branches are realized that uniquely deliver circuit response and output. For some circuits, and due to the operating characteristics of the switch elements, additional circuit elements, or stages, must be incorporated to prevent "back biasing." SUS-LOC is fully active. Only active elements perform logic synthesis and those components not directly related to logic synthesis, such as resistors and/or other passive loads, are relegated the task of circuit protection. The fabrication of r-valued, multi-valued, or multiple-valued logic circuits, designed using the definitions of the SUS-LOC structure can be accomplished with known techniques, materials, and equipment.

Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities

Abstract: A semiconductor device including a logic array having a multiplicity of identical logic cells, each identical logic cell comprising at least one look-up table, a metal connection layer overlying the multiplicity of identical logic cells for providing a permanent customized interconnect between various inputs and outputs thereof.

Method for programming an FPGA and implementing an FPGA interconnect

Abstract: An apparatus comprising a plurality of register logic circuits, a core circuit, a memory circuit, and a plurality of logic circuits. The register logic circuits may each be configured to generate a first logic signal in response to (i) an input data signal, (ii) a second logic signal, (iii) a first clock signal and (iv) a second clock signal. The core circuit may be configured to generate a plurality of data signals and a first control signal in response to the first logic signals and a second control signal. The memory may be configured to present the second control signal to the core circuit. The logic circuits may each be configured to present the second logic signal in response to the first logic signal and the data signals. An embedded FPGA core may be enabled to provide an interconnect to a chip. Additionally, software may enable a wide variety of features including bug fixes and product variations, all without changing the silicon.