Showing papers on "Pass transistor logic published in 2001"

Logic circuits with carbon nanotube transistors

Abstract: We demonstrate logic circuits with field-effect transistors based on single carbon nanotubes. Our device layout features local gates that provide excellent capacitive coupling between the gate and nanotube, enabling strong electrostatic doping of the nanotube from p-doping to n-doping and the study of the nonconventional long-range screening of charge along the one-dimensional nanotubes. The transistors show favorable device characteristics such as high gain (>10), a large on-off ratio (>10(5)), and room-temperature operation. Importantly, the local-gate layout allows for integration of multiple devices on a single chip. Indeed, we demonstrate one-, two-, and three-transistor circuits that exhibit a range of digital logic operations, such as an inverter, a logic NOR, a static random-access memory cell, and an ac ring oscillator.

Low-voltage low-power CMOS full adder

Abstract: Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented.

Robust subthreshold logic for ultra-low power operation

Abstract: Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic.

Dynamic current mode logic (DyCML): a new low-power high-performance logic style

Abstract: This paper introduces a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. Unlike CML circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery-powered systems. Simulation and test results show that DyCML circuits are superior to other logic styles in terms of power and delay. A 16-bit DyCML carry look-ahead adder (CLA), fabricated in 0.6-/spl mu/m CMOS technology, attains a delay of 1.24 ns and dissipates 19.2 mW at 400 MHz.

Memory circuit for use in hardware emulation system

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

0.18-/spl mu/m CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation

Abstract: A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-/spl mu/m CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors.

Merged logic and memory combining thin film and bulk Si transistors

Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips The memory cells use three-dimensional (3D) SRAM structures Two kinds of 3D logic cells are disclosed 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture A high density “system on chip” architecture is described The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described

QSERL: quasi-static energy recovery logic

Abstract: A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8/spl times/8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz.

MTCMOS sequential circuits

Abstract: Multi-threshold CMOS is an increasingly popular circuit technique that enables high performance and low power operation, but requires sequential circuit structures that can retain state during standby modes. This work presents an in depth analysis of potential leakage paths, and yields several efficient MTCMOS flip flop implementations including a novel approach that utilizes a leakage feedback gate to enable state retention during standby modes in dynamic flip flops.

Programmable logic array with vertical transistors

Abstract: A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

CMOS gate array with vertical transistors

Abstract: Structures and methods for CMOS gate arrays with vertical transistors are provided. The CMOS gate arrays with vertical transistors comprise a logic circuit. The logic circuit includes a dynamic pull-down circuit having a number of logic inputs, a clock input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock input is coupled to a gate of a free standing vertical p-channel transistor for precharging the output. The logic circuit further includes a static pull-up circuit having a number of logic inputs, a clock bar input, and an output. The number of logic inputs are coupled to a number of gates of free standing vertical n-channel transistors. The clock bar input is coupled to a gate of a free standing vertical n-channel transistor for precharging the output. And, the dynamic pull down circuit is cascaded with the static pull up circuit such that one of the number of inputs for the pull up circuit is coupled to the output of the pull down circuit.

High-speed low-power adder with a new logic style: pseudo dynamic logic (SDL)

Abstract: In this paper, a high speed and low power adder is designed using a new logic-design style called Pseudo Dynamic Logic (SDL). Traditional dynamic logic is pre-charged to a default value and in the evaluation phase is changed to its real logic, However, in this new logic style, the internal nodes are charged to an intermediate pre-charge value, so that the evaluation is performed faster. A 32-bit CLA adder has been designed and simulated using HSPICE Level 49 parameters of a 0.6 /spl mu/m CMOS process. Simulated measurements on this adder show that the worst-case delay is 1.56 ns. This shows 2.1 times speed improvement and 21.2% area saving in comparison to a domino dynamic logic design implemented with the same technology.

Output circuit for a transmission system

Abstract: An output circuit for a transmission system includes an input terminal receiving an input logical signal, a first output terminal outputting a first output logical signal having a logic corresponding to a logic of the input logical signal, a second output terminal outputting a second output logical signal having a logic corresponding to an inverted logic of the input logical signal, a first constant voltage supply circuit generating a first voltage level, a second constant voltage supply circuit generating a second voltage level, and an output logic formation circuit connected to the first and second constant voltage supply circuits. The output logic formation circuit generates the first and second output logical signals having either the first voltage level or second voltage level based on the logic of the input logical signal.

A multiple-valued logic with merged single-electron and MOS transistors

Abstract: Proposes merged single-electron and MOS devices that serve as basic components of multiple-valued logic, such as a universal literal gate and a quantizer. We verified their operation by using single-electron transistors and MOSFETs fabricated on the same wafer by pattern-dependent oxidation process. We also discuss their application to an analog-to-digital converter and a multiple-valued adder.

Current-controlled CMOS circuits with inductive broadbanding

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding /C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding /C3MOS /CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits

Abstract: We introduce a Reversible Programmable Gate Array (RPGA) based on regular structure to realize binary functions in reversible logic. This structure, called a 2 * 2 Net Structure, allows for more efficient realization of symmetric functions than the methods shown by previous authors. In addition, it realizes many non-symmetric functions even without variable repetition. Our synthesis method to RPGAs allows to realize arbitrary symmetric function in a completely regular structure of reversible gates with smaller “garbage” than the previously presented papers. Because every Boolean function is symmetrizable by repeating input variables, our method is applicable to arbitrary multi-input, multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of garbage gate outputs. The method can be also used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.

Emulation circuit with a hold time algorithm, logic analyzer and shadow memory

Abstract: A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

Microprocessor resistant to power analysis

Abstract: A secure microprocessor is designed using quad-coded logic which is similar to dual-rail encoded asynchronous logic except that the '11' state propagates an alarm. The alarm signal obliterates secure data in its path. Quad-coded logic provides resilience to power glitches and single-transistor or single-wire failures. The already low data dependency of the power consumption makes power analysis attacks difficult, and they are made even more difficult by inserting random delays in data and control paths, and by a set-random-carry instruction which enables software to make a non-deterministic choice between equivalent instruction sequences. These features are particularly easy to implement well in quad-coded logic.

Regenerative signal level converter

Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C 3 MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a CMOS latch.

Level shifter for use in active matrix display apparatus

Abstract: Between a positive power supply 18 and a negative power supply 19 , a p-channel transistor 11 and an n-channel transistor 14 are connected in series while a p-channel transistor 12 and an n-channel transistor 15 are also connected in series. An inverted input signal *Sig 1 is input to the respective gates of the transistors 11 and 14 , while an input signal Sigl is input to the respective gates of the transistors 12 and 15 . As a result, of a pair of the transistors connected in series, namely either the transistors 11 and 14 or the transistors 12 and 15 , when one transistor turns ON, the other transistor turns OFF. Thus, generation of through currents is prevented.

Logic architecture for single event upset immunity

Abstract: An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn't affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs. The dual to single path converter is coupled to receive signals output by the dual path logic gate. In the event that a transient signal appears at an input of the dual to single path converter, a current path may be interrupted, and a correct output signal value is maintained as a result of stray capacitance present at an output node.

Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Abstract: Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.

Differential CMOS logic with dynamic bias

Abstract: A CMOS circuit arrangement. In this arrangement, relatively thick oxide devices are fabricated along with relatively thin oxide devices on the same chip. High speed logic circuits are fabricated with thin oxide devices as differential logic operating with a low voltage swing. A current source is fabricated using thick oxide devices to drop a large percentage of the supply voltage, protecting the thin oxide devices from damage caused by large voltage swings. An adaptive bias control circuit receives inputs from the logic circuit or elsewhere to control the bias current available from the current source to permit larger currents to pass through the current source at switching times.

A practical floating-gate Muller-C element using vMOS threshold gates

Abstract: This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation.

Skew-tolerant high-speed (STHS) domino logic

Abstract: This paper presents skew-tolerant high-speed domino logic. Skew-tolerant high-speed domino logic resolves the floating dynamic node problem of high-speed domino logic and alleviates the strict clock timing requirement. Simulation results show that skew-tolerant high-speed domino logic is more robust to noise and timing variation than high-speed domino logic, while achieving better performance.

Programmable logic device having integrated probing structures

Abstract: A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

Designing fast asynchronous circuits

Abstract: A five-step design process for asynchronous circuits helps simplify their logic and speed their operation. First, assume that all logic gates in the control will have nearly uniform delay. Second, use the uniform delay assumption to simplify control logic. Third, lay out the chip to get wire length data. Fourth, choose a specific delay and calculate transistor widths to apply that specific delay uniformly to all logic gates in the control; this paper shows how. Fifth, verify correct operation with standard methods. The specific gate delay trades off speed, area, and power consumption; postponing its choice takes advantage of asynchrony to accommodate the limitations imposed by layout. The theoretical lower bound for specific delay depends on the logical effort of the most complex loop in the design and remarkably, is independent of wire capacitance, given wide enough transistors, but wire capacitance puts practical bounds on speed. The effect of wire resistance remains unexplored.

Dual threshold gate array or standard cell power saving library circuits

Abstract: A method is disclosed wherein a subset of logic blocks on an ASIC simiconductor logic chip is examined for replacement by functionally equivalent logic blocks in the ASIC library. The functionally equivalent logic block replacements are designed to exhibit, on average, significantly less subthreshold leakage currents. The replacement blocks are slower performing blocks, and therefore, checks are made to ensure that timing requirements are not violated.

Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

Abstract: Sub-threshold static and ratioed logic have recently been proposed to satisfy the ultra-low power requirement in applications such as hearing aids, pace-makers, wearable wrist-watch computers etc. These logic circuits, however, can be operated only at lower frequencies due to lower supply voltage. To increase the frequency of operation, we propose sub-threshold dynamic logic: Sub-Domino logic. A standard full-adder circuit is implemented in both Sub-Domino and Sub-CMOS logic operating in the subthreshold region. Simulation results show that Sub-Domino logic has lower power consumption, smaller area (60% of Sub-CMOS logic), and is 3 times faster than Sub-CMOS logic. It is also shown that Sub-Domino logic has excellent noise margin.

Dynamic memory word line driver scheme

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels V ss and V dd , and for providing a select signal at levels V ss and V dd , a high voltage supply source V pp which is higher in voltage than V dd , a circuit for translating the select signals at levels V ss and V dd to levels V ss and V pp and for applying it directly to the word lines whereby an above V dd voltage level word line is achieved without the use of double boot-strap circuits.