Showing papers on "Pass transistor logic published in 2002"

Modeling the effect of technology trends on the soft error rate of combinational logic

Abstract: This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards

Abstract: To protect security devices such as smart cards against power attacks, we propose a dynamic and differential CMOS logic style. The logic operates with a power consumption independent of both the logic values and the sequence of the data. Consequently, it will not reveal the sensitive data in a device. We have built a set of logic gates and flip-flops needed for cryptographic functions and compared those to Static Complementary CMOS implementations.

Deoxyribozyme-based logic gates.

Abstract: We report herein a set of deoxyribozyme-based logic gates capable of generating any Boolean function. We construct basic NOT and AND gates, followed by the more complex XOR gate. These gates were constructed through a modular design that combines molecular beacon stem-loops with hammerhead-type deoxyribozymes. Importantly, as the gates have oligonucleotides as both inputs and output, they open the possibility of communication between various computation elements in solution. The operation of these gates is conveniently connected to a fluorescent readout.

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

Abstract: Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.

Semiconductor integrated circuit device having power reduction mechanism

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Configurable logic element with expander structures

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Ferroelectric non-volatile logic elements

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Nanocell logic gates for molecular computing

Abstract: Molecular electronics seeks to build electrical devices to implement computation - logic and memory - using individual or small collections of molecules. These devices have the potential to reduce device size and fabrication costs, by several orders of magnitude, relative to conventional CMOS. However, the construction of a practical molecular computer will require the molecular switches and their related interconnect technologies to behave as large-scale diverse logic, with input/output wires scaled to molecular dimensions. It is unclear whether it is necessary or even. possible to control the precise regular placement and interconnection of these diminutive molecular systems. This paper describes genetic algorithm-based simulations of molecular device structures in a nanocell where placement and connectivity of the internal molecular switches are not specifically directed and the internal topology is generally disordered. With some simplifying assumptions, these results show that it is possible to use easily fabricated nanocells as logic devices by setting the internal molecular switch states after the topological molecular assembly is complete. Simulated logic devices include an inverter, a NAND gate, an XOR gate and a 1-bit adder. Issues of defect and fault tolerance are addressed.

SOI DRAM having P-doped poly gate for a memory pass transistor

Abstract: An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.

Field programmable logic arrays with vertical transistors

Abstract: A field programmable logic array with vertical transistors having single or split control lines is used to provide logical combinations responsive to an input signal. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the field programmable logic array. The field programmable logic array is programmed in the field to select a particular logic combination responsive to a received input signal. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F2 is needed per bit of logic, where F is the minimum lithographic feature size.

Designing multiplier blocks with low logic depth

Abstract: The depth of logic in an integrated circuit, particularly a CMOS circuit, is highly correlated both with power consumption and degraded switching speed. Hence, designs with low logic depth can aid in reducing power consumption and increasing switching speed. In this paper we demonstrate how new and modified algorithms have been used to design multiplier blocks with low logic depth and power consumption.

Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D/sup 3/L (D/sup 4/L) logic styles

Abstract: In this paper, a new family of dynamic logic gates called Dual-rail Data-Driven Dynamic Logic (D/sup 4/L) is introduced. In this logic family, the synchronization clock signal has been eliminated and correct precharge and evaluation sequencing is maintained by appropriate use of data instances. The methodology and characteristics of D/sup 4/L are demonstrated in the design of a CLA 32-b adder and a 17-b high-speed multiplier. Based on VHDL simulations, the D/sup 4/L implemented 32-b adder has 23% less switching-activity than a comparable domino adder and for D/sup 4/L multiplier switching-activity is 14.5% less than its domino rival. HSPICE simulation in a 0.6 /spl mu/m CMOS process shows that D/sup 4/L has a 17% power saving over domino in a 32-b CLA adder design and a 10% saving in a 17-b multiplier design while a D/sup 4/L adder has 8% less delay than a domino one.

Programmable logic circuit device having look up table enabling to reduce implementation area

Abstract: A programmable logic circuit device has a plurality of logic blocks, a plurality of routing wires, a plurality of switch circuits, a plurality of connection blocks, and an I/O block performing an input/output operation with external equipment. The routing wires are connected to each of the logic blocks, the switch circuits are provided at an intersection of each of the routing wires, and the connection blocks are provided between an I/O line of each of the logic blocks and each of the routing wires. Each of the logic blocks has a look up table of M inputs and N outputs, which has a plurality of LUT units; and an internal configuration control circuit controlling an internal configuration of the plurality of LUT units.

Impact of technology scaling on CMOS logic styles

Abstract: In this paper, the main challenges of technology scaling are reviewed in depth Five popular logic families namely; conventional CMOS, complementary pass logic, Domino, differential cascode voltage switch logic, and current mode logic are presented, highlighting their advantages and drawbacks The behavior of each logic style in deep submicrometer technologies is analyzed and predicted for future technology generations To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder The circuits were implemented in 08-, 06-, 035-, and 025-/spl mu/m CMOS technologies, and optimized for minimum energy-delay product

Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family

Abstract: In this paper, a new logic-design style called Pseudo Dynamic Logic (SDL) is introduced. In this logic-design style, the internal nodes of the logic circuits are not precharged to high or low values, rather the initial charges on nodes are shared to yield an intermediate precharge value for faster evaluation. A 32-bit adder has been designed and simulated using HSPICE Level-49 parameters of a 0.6 /spl mu/m CMOS process. Simulated measurements on this adder show that the worst-case delay is 1.56 ns. This demonstrates 2.1 times speed improvement in comparison to a domino dynamic logic design implemented with the same technology.

SRAM bus architecture and interconnect to an FPGA

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

A low power and reduced area carry select adder

Abstract: A carry select adder (CSA) can be implemented by using a single adder block and an add-one circuit instead of using dual adder blocks. The add-one circuit is based on "first" zero detection logic and a few multiplexers. In the modified CSA, one of the n-bit adder blocks is replaced by an add-one circuit consisting of fewer transistors. This scheme considerably reduces the power and area, with negligible speed penalty. For 8-bit length, n=8, this modified CSA requires 38% fewer transistors and consumes only 73% of the power, compared to the conventional design, using a 0.5 /spl mu/m CMOS technology.

Fan speed controller with conditioned tachometer signal

Abstract: The speed of a fan motor is controlled by varying a DC voltage to the fan motor. A series pass transistor is used to vary the DC voltage to the fan motor. A power management controller sets the fan motor speed by outputting pulses to a pulse-to-DC voltage converter that changes the pulses to a proportional DC control voltage for controlling the series pass transistor. A tachometer output amplifier circuit is used to remove DC components and amplify to useful logic levels a low level tachometer output signal from the fan motor. The amplified tachometer signal is used by the power management controller in controlling the rotational speed of the fan motor.

Programmable latch array using antifuses

Abstract: A latch includes an inverter; a pass transistor having a first terminal coupled to an input of the inverter and a second terminal coupled to a programming voltage; a first capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a first predetermined voltage; and a second capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a second predetermined voltage; wherein each of the first and second capacitors uses an antifuse.

Current-controlled CMOS logic family

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C 3 MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C 3 MOS logic with low power conventional CMOS logic. The combined C 3 MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Low drop-out voltage regulator

Abstract: An LDO regulator is arranged to provide regulation with a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance.

Data-driven clock gating for a sequential data-capture device

Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.

Intelligent data management fo hard disk drive

Abstract: Power control logic in a disk drive controls a mode of operation of operational logic of the disk drive for reduced power consumption. The operational logic includes a first and a second mode of operation, such that the second mode of operation consumes less power than the first mode of operation. The power control logic includes a memory, and is coupled to communication signals over an interface. In response to a predetermined communication signal, the power control logic configures the memory for storing data that is related to the predetermined communication signal.

Binary adders of multigate single-electron transistors: specific design using pass-transistor logic

Abstract: We describe how to construct area-efficient adders using single-electron transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to single-electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.

A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature

Abstract: A high-performance and low-power 32-bit multiply-accumulate unit (MAC) is described in this paper. The last mixed-length encoding scheme used in the MAC leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace tree of a 12-bit encoding scheme. With this new encoding scheme, one-cycle throughput for 16-bit /spl times/16-bit and 32-bit /spl times/16-bit MAC instructions was achieved at very high frequencies. To handle media streams more efficiently, the single-instruction-multiple-data (SIMD) and the multiply-with-implicit-accumulate (MIA) features were added. A mixture of static CMOS logic and complementary pass-gate logic (CPL) was used to achieve the high-speed and low-power goals. Several power-saving techniques were also implemented in this MAC.

Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit

Abstract: A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.

Method and apparatus for controlling and observing data in a logic block-based asic

Abstract: A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. In normal mode, a logic block can implement combinational, sequential, or other functions and still later be as a master-slave flip-flop. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage.

Semiconductor device with multiple power sources

Abstract: Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C 3 MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C 3 MOS logic with low power conventional CMOS logic. The combined C 3 MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C 3 MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.