Showing papers on "Pass transistor logic published in 2003"

VLSI implementations of threshold logic-a comprehensive survey

Abstract: This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

Regular logic fabrics for a via patterned gate array (VPGA)

Abstract: Standard-cell-based ASIC costs are increasing so rapidly that fewer products have the volume required to justify NRE costs. Consequently, more designs are relying on programmable devices, such as FPGAs, which have inferior power-delay performance. We propose to explore new regular logic fabrics that are customizable by a few via masks to provide implementation simplicity and NRE costs comparable to an FPGA, but with power-delay performance closer to an ASIC. This paper describes the design of lookup tables (LUTs) similar to those used in FPGAs, but restructured for via-patternability and performance. Results demonstrate power-delay performance comparable to complex-function standard cells, but inferior performance compared to simple logic gates. We compare several logic block designs based on our heterogeneous regular logic fabrics with those constructed using standard cells.

A novel hybrid pass logic with static CMOS output drive full-adder cell

Abstract: A novel design of a 1-bit full adder cell featuring a hybrid CMOS logic style is proposed. The simultaneous generation of XOR and XNOR outputs by pass logic is advantageously exploited in a novel complementary CMOS stage to produce full-swing and balanced outputs so that adder cells can be cascaded without buffer insertion. The increase in transistor count of the complementary CMOS stage is compensated by its reduction in layout complexity. Comparing with other 1-bit adder cells using different but uniform logic styles, simulation results show that it is very power efficient and has lower power-delay product over a wide range of voltages.

A 1.3GHz fifth generation SPARC64 microprocessor

Abstract: A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 34.7W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error detection and recovery mechanism is implemented for execution units and data path logic circuits in addition to on-chip arrays to detect and recover from data logic error. This processor is developed by using mostly in-house CAD tools.

A model for transient fault propagation in combinatorial logic

Abstract: Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional HSPICE like simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a novel mathematical model to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit, which is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to HPSICE. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Abstract: Dramatic increase of subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Current models have been developed based on the exact device geometry, 2-D doping profile and operating temperature. A circuit level model of junction BTBT leakage (which is unprecedented) has been developed. Simple models of the subthreshold current and the gate current have been presented. Here, for the first time, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a sum of current sources (SCS). The SCS transistors model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25nm effective length) at the room and at the elevated temperatures.

High-performance and power-efficient CMOS comparators

Abstract: Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.

Logic circuits based on carbon nanotubes

Abstract: We demonstrate logic circuits with field-effect transistors based on single carbon nanotubes. A new technique is used for achieving local gates in nanotube field-effect transistors that provide excellent capacitive coupling between the gate and nanotube, enabling the transistor to be ambipolar. The transistors show favorable device characteristics such as a high gain, a large on-off ratio, and room-temperature operation. Importantly, it also allows for the integration of multiple devices on a single chip. Indeed, we demonstrate 1-, 2-, and 3-transistor circuits that exhibit a wide range of digital logic operations such as an inverter, a logic NOR, and an AC ring oscillator.

Reversible logic synthesis for minimization of full-adder circuit

Abstract: Reversible logic is of the growing importance to many future technologies. A reversible circuit maps each output vector, into a unique input vector, and vice versa. This paper introduces an approach to synthesise the generalized multi-rail reversible cascades and minimizing the "garbage bit" and number of reversible gates, which is the main challenge of reversible logic synthesis. This proposed full-adder circuit contains only three gates and two garbage outputs whereas earlier full-adder circuit by M. Perkowski et al. (2001) requires four gates and produces two garbage outputs and another existing full-adder circuit by Md. H. H Azad Khan (2002) requires three gates but produces three garbage outputs. Thus, the proposed full-adder circuit is efficient in terms of number of gates with compared to M. Perkowski et al. (2001) as well as in terms of number of garbage outputs with compared to Md. H. H Azad Khan (2002).

Low skew clock input buffer and method

Abstract: An input buffer includes first and second cross-coupled differential amplifiers. Each amplifier drives a buffer signal from a first logic state to a second logic state at a first slew rate when an input signal transitions from a first logic state to a second logic state and a complementary input signal transitions from the second logic state to the first logic state, and drives the buffer signal from the second logic state to the first logic state at a second slew rate when the input signal transitions are the complement of these previous transitions. An output circuit generates a first edge of an output signal when the buffer signal from the first amplifier transitions from the first logic state to the second logic state and generates a second edge of the output signal when the buffer signal from the second amplifier transitions from the first to the second logic state.

Ultra-low quiescent current low dropout (LDO) voltage regulator with dynamic bias and bandwidth

Abstract: An LDO regulator automatically switches from the SLEEP mode to the ON mode without the need for an externally generated control signal. The LDO regulator utilizes a pair of drive amplifiers to drive a SLEEP mode pass transistor and a normal ON mode pass transistor, respectively. The regulator also has a circuit for adjusting the bias applied to the amplifiers for each mode of operation.

Logic and memory with nanocell circuits

Abstract: Molecular electronics is an emerging field that seeks to build faster, cheaper, denser computers from nanoscale devices. The nanocell is a molecular electronics design wherein a random, self-assembled array of molecules and metallic nanoparticles is addressed by a relatively small number of input/output pins. The challenge then is to program the nanocell post-fabrication. We have previously demonstrated the ability to program individual simulated nanocells as logic gates. In this paper, we further explore the problem of programming nanocells and consider connecting nanocells into circuits using bistable latches at the interconnects. These latches are critical because they permit signal restoration. Simulated nanocell circuits for logic and memory are presented here.

Timing Analysis in Presence of Power Supply and Ground Voltage Variations

Abstract: Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Abstract: A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-/spl mu/m ferroelectric/CMOS.

Spatial light modulator with charge-pump pixel cell

Abstract: A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the gate of said access transistor is connected to a wordline, and wherein the drain of said access transistor is connected to a first plate of said storage capacitor forming a storage node, and wherein the second plate of said storage capacitor is connected to a pump signal. This arrangement allows for a novel pixel circuit design with area requirements comparable to that of a 1T1C DRAM-like pixel cell, but with the advantage of an output voltage swing of the full range allowed by the breakdown voltage of the pass transistor. A spatial light modulator such as a micromirror array can comprise such a voltage storage cell.

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

Abstract: In this paper we present novel recharged logic for multiple-valued (MV) systems by utilizing semi-floating-gate (SFG) transistors. The recharged multiple-valued logic can be used to implement low-power digital circuits. The improvement in power dissipation is mainly in reduced dynamic power dissipation. The main purpose is to level out the power dissipated by a digital system to obtain more suitable logic for mixed mode design.

Low-leakage integrated circuits and dynamic logic circuits

Abstract: An integrated circuit is disclosed that includes one or more blocks of switching logic (101, 103) ( comprised of transistors) connected between a power supply (VDD) and a common node (GNDV). A control transistor (M) connects the common node (GNDV) to ground. The control transistor (M) has a higher threshold voltage level than the voltage threshold level(s) of the transistors that comprise the switching logic blocks (101, 103). A bias generator (100) provides a positive bias to the body of the control transistor (M) when the control transistor is "on". Further disclosed is an integrated circuit comprising a first plurality of serially connected transistors (M1, M2,M3, and M4) establishing a first current path from a voltage source (VDD) to ground and a second plurality of serially connected transistors (M5, M6) establishing a second current path from the voltage source (VDD) to ground. The first and second plurality of transistors each includes at least one high-threshold transistor. The integrated circuit further includes a means (201) for decreasing a resistance level of the high threshold transistors when the high threshold transistors are on.

Multi-threshold threshold logic circuit design using resonant tunnelling devices

Abstract: A novel and extremely compact circuit topology able to implement a generalised threshold logic function with two thresholds is presented The circuit consists of resonant tunnelling diodes and heterostructure field effect transistors

Fredkin/Toffoli Templates for Reversible Logic Synthesis

Abstract: Reversible logic has applications in quantum computing, low power CMOS, nanotechnology, optical computing, and DNA computing. The most common reversible gates are the Toffoli gate and the Fredkin gate. Our synthesis algorithm first finds a cascade of Toffoli and Fredkin gates with no backtracking and minimal look-ahead. Next we apply transformations that reduce the size of the circuit. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence in the network to be synthesized matches more than half of a template, then a transformation that reduces the gate count can be applied. In this paper we show that Toffoli and Fredkin gates behave in a similar manner. Therefore, some gates in the templates may not need to be specified-they can match a Toffoli or a Fredkin gate. We formalize this by introducing the box gate. All templates with less than six gates are enumerated and classified. We synthesize all three input, three output reversible functions and compare our results to those obtained previously.

Ultra-low quiescent current low dropout (LDO) voltage regulator with dynamic bias and bandwidth

Abstract: An LDO regulator automatically switches from the SLEEP mode to the ON mode without the need for an externally generated control signal. The LDO regulator utilizes a pair of drive amplifiers to drive a SLEEP mode pass transistor and a normal ON mode pass transistor, respectively. The regulator also has a circuit for adjusting the bias applied to the amplifiers for each mode of operation.

Digital logic with reduced leakage

Abstract: A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

Optical logic gates using semiconductor optical amplifiers

Abstract: All-Optical logic can avoid expensive demultiplexing back to electronics in telecommunications. The term all-optical is used to described processing in which all signal paths are optical whether used for control or information. Semiconductor optical amplifiers (SOAs) can perform all optical logic because they have nonlinearity, low latency, and require low power. We use highly accurate computer models to simulate and evaluate NOR and NXOR logic gates using SOAs. These elements can act as building blocks for advanced logic systems. For example, in previous publications we described an approach to constructing arithmetic units form optical logic elements.

Design and analysis of low-voltage current-mode logic buffers

Abstract: This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter. It is shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

Controlling operation of a voltage supply according to the activity of a multi-core integrated circuit component or of multiple IC components

Abstract: A voltage supply is to power an integrated circuit (IC) component of a computer system. The component has a number of logic cores or functional blocks that are powered by the voltage supply. Each logic core can operate in multiple work capability states. Operation of the voltage supply is then controlled according to a combination of the work capability states in which the logic cores are actually operating.

Timing optimization of FPGA placements by logic replication

Abstract: Logic replication for placement level timing optimization is studied in the context of FPGAs. We make the observation that critical paths are dominated by interconnect delay and are frequently highly circuitous. We propose a systematic replication technique to "straighten" such paths. The resulting algorithm has several components: cell selection, slot selection for a duplicate cell, fanout partitioning and placement legalization. This algorithm is described and promising preliminary experimental results are reported with up to 29% improvement in critical path delay.

Inverter, semiconductor logic circuit, static random access memory and data latch circuit

Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

I2C device including bus switches and programmable address

Abstract: An I 2 C device is disclosed that includes a main I 2 C section, bus switches, switch logic, and address logic as part of the I 2 C device. The I 2 C device is coupled to an I 2 C bus for communicating with other I 2 C devices and an I 2 C bus controller that is also on the I 2 C bus. The switch logic controls a current position of the switches. The I 2 C device is coupled to the I 2 C bus utilizing the switches. The switches control whether the main I 2 C section, the address logic, the switch logic, or a combination of the main I 2 C section, address logic, and switch logic is currently coupled to I 2 C bus. The switches also can be used, if desired to remove from the buss all devices that are downstream from a given device containing switches. The address logic is used to receive and store the address of the I 2 C device. The I 2 C device will respond to the address that is stored in its address logic.

Performance-driven mapping for CPLD architectures

Abstract: We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop several techniques for area reduction, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA packing. We compare PLAmap with a previous algorithm TEMPLA (Anderson and Brown 1998) and a commercial tool Altera Multiple Array MatriX (MAX) + PLUS II (Altera Corporation 2000) using Microelectronics Center of North Carolina (MCNC) benchmark circuits. With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.