Showing papers on "Pass transistor logic published in 2004"

Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

Abstract: This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.

A 180mV FFT processor using subthreshold circuit techniques

Abstract: Minimizing energy requires scaling supply voltages below device thresholds. Logic and memory design techniques allowing subthreshold operation are developed and demonstrated. The fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.

Organic complementary-like inverters employing methanofullerene-based ambipolar field-effect transistors

Abstract: We demonstrate a complementary-like inverter comprised of two identical ambipolar field-effect transistors based on the solution processable methanofullerene [6,6]-phenyl-C61-butyric acid methyl ester (PCBM). The transistors are capable of operating in both the p- and n-channel regimes depending upon the bias conditions. However, in the p-channel regime transistor operation is severely contact limited. We attribute this to the presence of a large injection barrier for holes at the Au∕PCBM interface. Despite this barrier the inverter operates in both the first and third quadrant of the voltage output versus voltage input plot exhibiting a maximum gain in the order of 20. Since the inverter represents the basic building block of most logic circuits we anticipate that other complementary-like circuits can be realized by this approach.

The magic of a via-configurable regular fabric

Abstract: In this paper, we provide a comprehensive study of the mappability of a via-configurable gate array (VCGA). Although, the base cell of the VCGA is simple, by customizing only via masks it can implement various combinational logic functions, sequential elements, and SRAM cells. Our VCGA can be efficiently configured into SRAM arrays, adders and multipliers. The strong configurability of our VCGA allows us to minimize the number of fixed parts in a general-purpose VCGA fabric, which greatly improves area utilization.

A greedy algorithm for tolerating defective crosspoints in nanoPLA design

Abstract: Recent developments suggest both plausible fabrication techniques and viable architectures for building sublithographic programmable logic arrays using molecular-scale wires and switches. Designs at this scale will see much higher defect rates than in conventional lithography. However, these defects need not be an impediment to programmable logic design as this scale. We introduce a strategy for tolerating defective crosspoints and develop a linear-time, greedy algorithm for mapping PLA logic around crosspoint defects. We note that P-term fanin must be bounded to guarantee low overhead mapping and develop analytical guidelines for bounding fanin. We further quantify analytical and empirical mapping overhead rates. Including fanin bounding, our greedy mapping algorithm maps a large set of benchmark designs with 13% average overhead for random junction defect rates as high as 20%.

On circuit techniques to improve noise immunity of CMOS dynamic logic

Abstract: Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.

Evaluation of low-leakage design techniques for field programmable gate arrays

Abstract: In this paper we evaluate the trade-offs between various low-leakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15%-30%.

Cost-effective radiation hardening technique for combinational logic

Abstract: A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates that have the lowest logical masking probability to achieve cost-effective tradeoffs between overhead and soft error failure rate reduction. The technique, which decouples the physical from the logical aspects of soft error susceptibility of a gate, uses a gate (transistor) sizing technique that is both efficient and accurate (in comparison to SPICE). A full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.

Floating gate transistor with horizontal gate layers stacked next to vertical body

Abstract: Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will provide an indication of the stored data at this location in the memory array within the EEPROM or will act as the absence of a transistor at this location in the logic array within the FPLA. The memory array or the logic array includes densely packed cells, each cell having a semiconductor pillar providing shared source and drain regions for two vertical body transistors that have control gates overlaying floating gates distributed on opposing sides of the semiconductor pillar. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data or to represent a logic function, an area of only 2F 2 is needed per respective bit of data or bit of logic, where F is the minimum lithographic feature size.

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

Abstract: We designed a logic-library-friendly SRAM array. The array uses rectangular-diffusion cell (RD cell) and delta-boosted-array-voltage scheme (DBA scheme). In the RD cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA scheme compensates it. Using the combination of RD cell and DBA scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency, 140-/spl mu/W power dissipation, and 0.9-/spl mu/A standby current.

Superconducting digital electronics

Abstract: Single-flux quantum logic (SFQ) circuits, in which a flux quantum is used as an information carrier, have the possibility for opening the door to a new digital system operated at over 100-GHz clock frequency at extremely low power dissipation. The SFQ logic system is a so-called pulse logic, which is completely different from the level logic for semiconductors like CMOS, so circuit design technologies for SFQ logic circuits have to be newly developed. Recently, much progress in basic technologies for designing SFQ circuits and operating circuits at high speeds has been made. With advances in these design tools, large-scale circuits including more than several thousand junctions can be easily operated with the clock frequency of more than several tens of gigahertz. High-end routers and high-end computers are possible applications of SFQ logic circuits because of their high throughput nature and the low power dissipation of SFQ logic. In this paper, recent advances of SFQ circuit design technologies and recent developments of switches for high-end routers and microprocessors for high-end computers that are considered possible applications for SFQ logic will be described.

Improving the Security of Dual-Rail Circuits

Abstract: Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method.

Integrated circuit logic with self compensating block delays

Abstract: An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

Novel Reconfigurable Logic Gates Using Spin Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract: We propose and numerically simulate novel reconfigurable logic gates employing spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The output characteristics of the spin MOSFETs depend on the relative magnetization configuration of the ferromagnetic contacts for the source and drain, that is, high current-drive capability in parallel magnetization and low current-drive capability in antiparallel magnetization [S. Sugahara and M. Tanaka: Appl. Phys. Lett. 84 (2004) 2307]. A reconfigurable NAND/NOR logic gate can be realized by using a spin MOSFET as a driver or an active load of a complimentary MOS (CMOS) inverter with a neuron MOS input stage. Its logic function can be switched by changing the relative magnetization configuration of the ferromagnetic source and drain of the spin MOSFET. A reconfigurable logic gate for all symmetric Boolean functions can be configured using only five CMOS inverters including four spin MOSFETs. The operation of these reconfigurable logic gates was confirmed by numerical simulations using a simple device model for the spin MOSFETs.

Logic circuitry with shared lookup table

Abstract: A particular embodiment of the present invention provides a shared-LUT logic circuit that provides the functionality of two (n+1)LUT logic circuits without requiring approximately twice the resources of two nLUT circuits. In some embodiments, a shared-LUT logic circuit is provided that can be configured to operate in multiple modes including, for example, an nLUT mode, an (n+1)LUT mode, and other modes.

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Abstract: Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

On universality of general reversible multiple-valued logic gates

Abstract: A set of p-valued logic gates (primitives) is called universal if an arbitrary p-valued logic function can be realized by a logic circuit built up from a finite number of gates belonging to this set. In this paper, we consider the problem of determining the number of universal single-gate libraries of p-valued reversible logic gates with two inputs and two outputs, under the assumption that constant signals can be applied to an arbitrary number of inputs. We have proved some properties of such gates and established that over 97% of ternary gates are universal.

Dynamic and differential cmos logic with signal-independent power consumption to withstand differential power analysis

Abstract: A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic typically has one charging event per clock cycle and the charging event does not depend on the input signals. The differential feature masks the in-put value because a precharged output nodes is discharged during the evaluation phase. The dynamic feature breaks the input sequence: the discharged node is charged during the subsequent precharge phase.

Synthesis and optimization of threshold logic networks with application to nanotechnologies

Abstract: We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and research on thedevelopment of synthesis methodologies to generate optimized networks utilizing these devices. Many nanotechnologies, such as resonant tunneling diodes (RTD) and quantum cellular automata (QCA), are capable of implementing threshold logic. While functionally correct threshold gates have been successfully demonstrated, there exists no methodology or design automation tool for general multi-level threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with about 60 multi-output benchmarks were performed, though the results of only 10 of them are reported in this paper because of space restrictions. They indicate that up to 77% reduction in gate count is possible when utilizing threshold logic, with an average reduction being 52%, compared to traditional logic synthesis. Furthermore, thesynthesized networks are well-balanced, and hence delay-optimized.

Pseudo CMOS dynamic logic with delayed clocks

Abstract: Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS logic gate includes a delayed enable clock transistor coupled to a source region of at least two input transistors. The dynamic pseudo-pMOS logic gate includes a delayed enable clock transistor coupled to a drain of at least two input transistors. None of the logic input devices are connected in series.

Novel nanoelectronic triodes and logic devices with TBJs

Abstract: In this letter, we demonstrate the realization of novel diodes, triodes, and logic gates with three-terminal ballistic junctions (TBJs) made from a semiconductor heterostructure. The approach exploits the ballistic nature of electron transport, which has emerged in the nanostructures. Importantly, we show that TBJs function as logic AND gates and can be used to construct other compound logic gates, such as NAND gates with voltage gain, when combined with a point contact (an inverter). The demonstrated devices show favorable characteristics such as low turn-on voltage in rectification and room-temperature operation.

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits

Abstract: In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.

Universal masking on logic gate level

Abstract: A concept of random masking of arbitrary logic circuits on the logic gate level is developed and several techniques are proposed. The results are important for protecting hardware implementations of cryptographic algorithms against side-channel attacks.

Method of reading multi-level NAND flash memory cell and circuit for the same

Abstract: The disclosed is a method of reading a multi-level NAND flash memory cell and a circuit for the same. The read circuit for the NAND flash memory device includes a NAND flash memory cell having multi-level information, a first page buffer for storing an upper-bit, a second page buffer for storing a lower bit, and pass transistor for changing information of the second page buffer according to a variation of the first page buffer. In accordance with the present invention, “00” or “01” information is read out by applying a first voltage to a word line of the cell. “00”, “01”, or “11” information is read out by applying a second voltage to the word line. A latch pass control signal is applied to a pass transistor. Thus, it is possible to read out “00”, “01”, “11”, or “10” information.

Online testable reversible logic circuit design using NAND blocks

Abstract: A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.

Modeling and evaluation of positive-feedback source-coupled logic

Abstract: Positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits Positive feedback allows for significantly reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters Spectre simulations by using a 035-/spl mu/m CMOS process confirm that the proposed models are sufficiently accurate in practical cases PFSCL gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4 The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation

Programmable voltage regulator configurable for double power density and reverse blocking

Abstract: A programmable voltage regulator configurable for reverse blocking and double power density is disclosed herein. The programmable voltage regulator includes an error amplifier that couples to receive a reference voltage. A first NMOS pass transistor connects between an auxiliary voltage input node and the output terminal of the voltage regulator, wherein the first NMOS pass transistor is biased by the output of the error amplifier. Connected between the source of the first NMOS pass transistor and the second input of the error amplifier, a feedback network provides feedback for the voltage regulator. A second NMOS pass transistor connects between the first power supply and the auxiliary voltage input node. Furthermore, an independent node control circuit biases the second NMOS pass transistor such that in a first mode of operation, a first control signal input is operable to receive a signal for controlling the second NMOS pass transistor during reverse battery condition. In a second mode of operation, independent node control circuit includes a second control signal input that is operable to couple to the output terminal of the error amplifier while simultaneously the first power supply rail is operable to couple to the output terminal of the voltage regulator to provide double power density.

Generation and distribution of a dual-redundant logic supply voltage for an electrical system

Abstract: A power supply device ( 20 ) for an electrical system generates a primary logic supply voltage signal and one or more backup logic supply voltage signals from a plurality of sources ( 22, 24 ). The primary and backup logic supply voltage signals are distributed throughout the electrical system to provide a redundant logic supply to various components ( 330 ).

Random number generation based on logic circuits with feedback

Abstract: A random binary sequence generator (105) for generating a random binary sequence (RRBS) adapted to be used for producing random numbers, comprising at least one logic circuit (115) corresponding to an associated finite-state machine having a statetransition function including states arranged to form cycles of states, wherein: the at least one logic circuit has a set of logic circuit inputs (In) and a set of logic circuit outputs (Out) fed back to said logic circuit inputs; the associated finite-state machine is autonomous and asynchronous; the state-transition function is void of loops; and any of the cycles of states has either a minimum length equal to three states, in case the cycle is stable, or a minimum length of two states, in case the cycle is meta-stable.

On-chip service processor

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.