Showing papers on "Pass transistor logic published in 2008"

Spin Wave Magnetic NanoFabric: A New Approach to Spin-Based Logic Circuitry

Abstract: We describe a magnetic nanofabric, which may provide a route to building reconfigurable spin-based logic circuits compatible with conventional electron-based devices. A distinctive feature of magnetic nanofabric is that a bit of information is encoded into the phase of the spin wave signal. This makes it possible to transmit information without the use of electric current and to utilize wave interference for useful logic functionality. The basic elements include voltage-to-spin-wave and wave-to-voltage converters, spin waveguides, a spin wave modulator, and a magnetoelectric cell. We illustrate the performance of the basic elements by experimental data and the results of numerical modeling. The combination of the basic elements leads us to construct magnetic circuits for NOT and majority logic gates. Logic gates such as AND, OR, NAND, and NOR are shown as the combination of NOT and reconfigurable majority gates. Examples of computational architectures such as a multibit processor and a cellular nonlinear network are described. The main advantage of the proposed magnetic nanofabric is its ability to realize logic gates with fewer devices than in CMOS-based circuits. Potentially, the area of the elementary reconfigurable majority gate can be scaled down to 0.1 mum2. We also discuss the disadvantages and limitations of the magnetic nanofabric.

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Abstract: This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates

Abstract: The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15 m and 0.35 m technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE. Keywords—XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

Ultrafast all-optical logic gate using a nonlinear optical loop mirror based multi-periodic transfer function

Abstract: A complete set of all-optical logic gate operations using a nonlinear-optical-loop-mirror-based multi-periodic transfer function is proposed. This scheme can operate all of sixteen two-input logic operations without changing configuration. We experimentally demonstrate AND, NAND, OR, NOR, XOR, and XNOR operations at 40 Gbit/s in a single configuration. We investigate the limitation of processing speed, and numerical simulation will show the feasibility of the processing speed up to 350 Gbit/s.

Increasing the noise margin in organic circuits using dual gate field-effect transistors

Abstract: Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage.

Ultra Low Voltage Level Shifters to Interface Sub and Super Threshold Reconfigurable Logic Cells

Abstract: Ultra-low power consumption often comes at the price of reduced performance for energy conscious electronics - particularly reconfigurable circuits. Operating devices at ultra-low voltage levels provides the lowest energy per operation, but can penalize the frequency of operation by several orders of magnitude. A more optimized approach is to segregate the logic based on performance requirements and use multiple voltage levels to supply separate voltage islands in an integrated circuit. The concept can be extended such that the low performance circuits can be supplied with a voltage below the threshold voltage of the transistor (i.e. subthreshold logic), however no analysis has been completed to date with regards to the performance and operation of the level shifters required for communication between voltage islands of such disparate levels. This paper compares a variety of existing level shifters as well as several proposed level shifters in the context of up-converting subthreshold signals to superthreshold levels.

Design and fabrication of MEMS logic gates

Abstract: This paper presents a novel design of MEMS logic gate that can perform Boolean algebra the same as logic devices that are composed of solid-state transistors. This MEMS logic gate design inherits all the advantages from MEMS switches and thus is expected to have more applications than MEMS switches. One unique feature of this device is that it can perform either NAND gate or NOR gate functions with the same mechanical structure but with different electrical interconnects. In a prototype design, the device is 250 µm long, 100 µm wide and has 1 µm gap. The experimental results show that this device can operate at 10/0 V and achieve the proposed logic functions. The resonant frequency of the device is measured roughly at 30 kHz. Due to no metal-to-metal contact in the current device, the logic functions of the design are verified through observations and video taping.

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18- $\mu$ m CMOS

Abstract: This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required so that considerable improvements in area and power overheads can be achieved. Moreover, its throughput becomes twice as high as that of QSERL when their frequencies of power clocks (PCs) are identical. Results on the impact of variation on CEPAL are provided. Comparison between CEPAL and other known low-power logic style achieving iso-performance, namely, subthreshold logic is also given. In order to demonstrate workability of the newly developed circuit, an 8-bit shift register, designed in the proposed techniques, has been fabricated in a TSMC 0.18-mum CMOS process. Both simulation and measurement results verify the functionality of such a logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.

An Introduction to Reversible Latches

Abstract: Reversible logic has been suggested as one solution to the problem of power consumption in today's electronic devices This paper addresses the issue of designing reversible latches and provides an overview and analysis of some proposed designs

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

Abstract: In this paper, a new leading-zero counter (or detector) is presented. New boolean relations for the bits of the leading-zero count are derived that allow their computation to be performed using standard carry-lookahead techniques. Using the proposed approach various design choices can be explored and different circuit topologies can be derived for the design of the leading-zero counting unit. The new circuits can be efficiently implemented either in static or in dynamic logic and require significantly less energy per operation compared to the already known architectures. The integration of the proposed leading-zero counter with the leading-zero anticipation logic is analyzed and the most efficient combination is identified. Finally, a simple yet efficient technique for handling the error of the leading-zero anticipation logic is also presented. The energy-delay behavior of the proposed circuits has been investigated using static and dynamic CMOS implementations in a 130-nm CMOS technology.

Cascadable adiabatic logic circuits for low-power applications

Abstract: There have been several strategies proposed to realise adiabatic circuits. Most of them require a clock signal and also its complement form. In this investigation, the authors we propose a family of adiabatic circuits, which consist of two branches and which enable control of charging and discharging of the capacitive load only by the input signal, work with single time varying supply and with no need of complementary inputs. A mathematical expression has been developed to explain the energy dissipation in our adiabatic inverter circuit. Measurements of energy drawn, recovered and dissipated have been carried out through simulation and, they are the same as obtained from the theoretical expression. In the proposed circuit, the input and output logic levels are approximately the same and can be used for building cascaded logic circuits. The energy saving in this family is to the tune of 50% compared with CMOS circuits constructed with similar circuit parameters, up to 250 MHZ. The authors have described the proposed inverter, NAND gates, NOR gates, adder circuits and JK flip-flop along with their simulation results.

Compensation of LDO regulator using parallel signal path with fractional frequency response

Abstract: A low drop out (LDO) voltage regulator (10) includes a pass transistor (MPpass) having a source coupled by an output conductor (4) to a load and a drain coupled to an input voltage to be regulated. An error amplifier (2) has a first input coupled to a reference voltage, a second input connected to a feedback conductor (4A), and an output coupled to a gate of the pass transistor. A parallel path transistor (MPpa) has a source coupled to the input voltage, a gate coupled to the output (3) of the error amplifier (2), and a drain coupled to the feedback conductor. A feedback resistor (Rf) is coupled between the feedback conductor and the output conductor.

Memory cell layout structure with outer bitline

Abstract: An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first gate electrode region for the first PU/PD and driver transistors, a second gate electrode region for the cell pass and buffer pass transistors, and a third gate electrode region for the second PU/PD transistor. The third gate electrode region and the cell pass transistor are coupled to the first storage node and the first gate electrode region is coupled to the second storage node. The buffer pass and driver transistors are coupled to a source/drain path of the cell pass transistor and the buffer pass transistor is coupled between a bitline (BL) node and the driver transistor.

High Speed Ultra Low Voltage CMOS inverter

Abstract: In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.

Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits

Abstract: This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.

Single-electron-based flexible multivalued logic gates

Abstract: Single-electron transistor (SET)-based multivalued (MV) not-AND (NAND) and not-OR (NOR) logic cells were implemented on a silicon-on-insulator chip. Depending on the ways of connecting two SETs with a field-effect transistor, the voltage transfer characteristics show typical NAND or NOR gate functions for various input voltages, which are binary, MV, and binary-MV mixed. Moreover, the switching functionality of our NAND (NOR) can convert to OR (AND) operation by simply adjusting their initial input voltages. These flexible two-input logic gates are expected to provide four basic arithmetic cells for the SET MV logic gate family.

Techniques for optimizing design of a hard intellectual property block for data transmission

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Nanoelectromechanical digital inverter

Abstract: A digital inverter formed by three carbon nanotubes (CNTs) extending vertically from a substrate, one CNT functioning as first source (S 1 ) and having a first logic signal applied to it, another CNT functioning as second source (S 2 ) and having a second logic signal applied to it, a third CNT functioning as gate (G), and disposed between the two sources (S 1 , S 2 ). A drain (D) contact is associated with the gate (G). A logic signal applied to the gate (G) causes one or the other of the sources (S 1 , S 2 ) to deflect, contacting the drain (D) and transferring its logic signal thereto—such as logic “0” on the gate resulting in logic “1” (from one of the sources) being transferred to the drain (D), and logic “1” on the gate resulting in logic “0” (from the other of the sources) being transferred to the drain (D).

Energy-Efficient, High Performance Circuits for Arithmetic Units

Abstract: Adders and multipliers are the most important arithmetic units in a general microprocessor and the major source of power dissipation. Various architecture styles exist to implement these units, each having their own merits and demerits. However, due to continuing integrating intensity and growing needs of portable devices, low power design is of prime importance. In addition, much power is dissipated due to a large number of spurious transitions on internal nodes in power hungry multiplier structures. We present a new full adder structure based on complementary pass transistor logic (CPL) which is faster and more energy efficient than the existing structures. We also propose a new technique of implementing multiplier circuit using decomposition logic which improves speed and reduces power consumption by reducing the spurious transitions on internal nodes. Combined with the new adder structure and the decomposition logic, there is substantial improvement in the performance of the multiplier structures. With the help of these state of the art designs, it would be possible to design highly power efficient processors, especially digital signal processors. We have used TSPICE for simulation in the TSMC 180 nm technology.

Low drop voltage regulator with instant load regulation and method

Abstract: An LDO regulator ( 10 ) produces an output voltage (Vout) by applying the output voltage to a feedback input ( 6 ) of a differential input stage ( 10 A) and applying an output ( 3 ) of the differential input stage to a gate of a first follower transistor (MP 4 ) having a source coupled to an input ( 8 ) of a class AB output stage ( 10 C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP 5 ) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN 5,6 ) having an output coupled to a current source (I 1 ) and a gate of an amplifying transistor (MN 7 ). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN 3 ), causing it to turn on a pass transistor (MP 3 ) of the output stage.

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

Abstract: A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-Vt) domino logic blocks which are arranged in a programmable logical array-like design style with pipelining is presented. The modified domino logic circuits employ dual-transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. Moreover, an nMOS transistor is inserted in the discharging path of the output inverter such that the modified domino logic can be properly applied in a pipeline structure to reduce the power consumption. The addition of two 8-bit binary operands is executed in two cycles. Not only is it proven to be also suitable for long adders, the dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.

A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

Abstract: Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage output and delay.

Semiconductor integrated circuit device and power control method thereof

Abstract: A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.

High-density logic techniques with reduced-stack multi-gate field effect transistors

Abstract: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.

Complementary symmetry nanowire logic circuits: experimental demonstrations and in silico optimizations.

Abstract: Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.

Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Modular chassis arrangement with redundant logic power delivery system

Abstract: A modular packet network device has a chassis in which multiple logic cards mate to the front side of an electrical signaling backplane. Logic power for the logic cards is supplied from a group of power converter cards that convert primary power to the logic voltages required by the logic cards. The power converter cards lie in a separate cooling path behind the backplane. Advantages achieved in at least some of the embodiments include removing primary power planes from the signaling backplane or portion of the backplane, providing redundant, upgradeable power modules whose individual failure does not cause logic card failure, and providing cool air to power converter circuits that would be subject to only heated air if located on the logic cards. Other embodiments are also described and claimed.