scispace - formally typeset
Search or ask a question

Showing papers on "Pass transistor logic published in 2010"


Journal ArticleDOI
08 Apr 2010-Nature
TL;DR: Bipolar voltage-actuated switches, a family of nonlinear dynamical memory devices, can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq.
Abstract: The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

1,642 citations


Journal ArticleDOI
TL;DR: In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature and previously proposed rule of thumbs to evaluate minimum voltage are theoretically justified.
Abstract: In this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is presented. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependence of DC behavior on design and device parameters. The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn -ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of pMOS/nMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology.

176 citations


Journal ArticleDOI
TL;DR: A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR, affords a path to the practical realization of a new generation of mechanical computers.
Abstract: We present a nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the resonator's operating parameters. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically "tuned" via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.

160 citations


Journal ArticleDOI
TL;DR: This paper proposes and design a novel scheme of Toffoli and Feynman gates in all-optical domain, described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations.
Abstract: In recent years, reversible logic has emerged as a promising computing paradigm having application in low-power CMOS, quantum computing, nanotechnology and optical computing. Optical logic gates have the potential to work at macroscopic (light pulses carry information), or quantum (single photons carry information) levels with great efficiency. However, relatively little has been published on designing reversible logic circuits in all-optical domain. In this paper, we propose and design a novel scheme of Toffoli and Feynman gates in all-optical domain. We have described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations. Semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometer (MZI) can play a significant role in this field of ultra-fast all-optical signal processing. The all-optical reversible circuits presented in this paper will be useful to perform different arithmetic (full adder, BCD adder) and logical (realization of Boolean function) operations in the domain of reversible logic-based information processing.

145 citations


Patent
26 Apr 2010
TL;DR: In this paper, a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.
Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

132 citations


Journal ArticleDOI
TL;DR: Comparisons between adders based on full adders from the prior art and the ULPFA version demonstrate that the development outperforms the static CMOS and the CPL full adder, particularly in terms of power consumption and PDP by at least a factor of two.
Abstract: In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of the optimized version, namely, the ULP full adder (ULPFA), are carried out versus the BBL-PT full adder and its counterparts in two well-known and commonly used logic styles, i.e., conventional static CMOS logic and complementary pass logic (CPL), in a 0.13-μm PD SOI CMOS with a supply voltage of 1.2 V, demonstrating power delay product (PDP) and static power performance that are more than four times better than CPL design. This could lead to tremendous benefit for multiplier application. The implementation of an 8-bit ripple carry adder based on the ULPFA is finally described, and comparisons between adders based on full adders from the prior art and our ULPFA version demonstrate that our development outperforms the static CMOS and the CPL full adders, particularly in terms of power consumption and PDP by at least a factor of two.

121 citations


Journal ArticleDOI
TL;DR: A concept of magnetic logic circuits engineering, which takes an advantage of magnetization as a computational state variable and exploits spin waves for information transmission and a library of logic gates consisting of magneto-electric cells and spin wave buses providing 0 or π phase shifts is proposed.
Abstract: We propose a concept of magnetic logic circuits engineering, which takes an advantage of magnetization as a computational state variable and exploits spin waves for information transmission. The circuits consist of magneto-electric cells connected via spin wave buses. We present the result of numerical modeling showing the magneto-electric cell switching as a function of the amplitude as well as the phase of the spin wave. The phase-dependent switching makes it possible to engineer logic gates by exploiting spin wave buses as passive logic elements providing a certain phase-shift to the propagating spin waves. We present a library of logic gates consisting of magneto-electric cells and spin wave buses providing 0 or p phase shifts. The utilization of phases in addition to amplitudes is a powerful tool which let us construct logic circuits with a fewer number of elements than required for CMOS technology. As an example, we present the design of the magnonic Full Adder Circuit comprising only 5 magneto-electric cells. The proposed concept may provide a route to more functional wave-based logic circuitry with capabilities far beyond the limits of the traditional transistor-based approach.

115 citations


Journal ArticleDOI
TL;DR: Results show with QD excited state and wetting layer serving as dual-reservoir of carriers, as well as the ultra fast carrier relaxation of the QD device, this scheme is suitable for high speed Boolean logic operations.
Abstract: A scheme to realize all-optical Boolean logic functions AND, XOR and NOT using semiconductor optical amplifiers with quantum-dot active layers is studied. nonlinear dynamics including carrier heating and spectral hole-burning are taken into account together with the rate equations scheme. Results show with QD excited state and wetting layer serving as dual-reservoir of carriers, as well as the ultra fast carrier relaxation of the QD device, this scheme is suitable for high speed Boolean logic operations. Logic operation can be carried out up to speed of 250 Gb/s.

102 citations


Patent
08 Oct 2010
TL;DR: In this paper, the authors propose a logic circuit with an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width.
Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

97 citations


Proceedings ArticleDOI
13 Dec 2010
TL;DR: The modified GDI logic is fully compatible for implementation in a standard CMOS process, and while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.
Abstract: In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is proposed. The GDI method enables the implementation of a wide range of complex logic functions using only two transistors. This method is suitable for the design of low-power logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As opposite to our originally proposed GDI logic, the modified GDI logic is fully compatible for implementation in a standard CMOS process. Simulations of basic GDI gates under process and temperature corners in 40nm CMOS process are shown and compared to similar CMOS gates. We show that while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.

81 citations


Patent
06 Oct 2010
TL;DR: In this paper, a transistor is formed using an oxide semiconductor in which the hydrogen concentration is 5×1019 (atoms/cm3) or lower, and leakage current of the transistor can be reduced.
Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Journal ArticleDOI
TL;DR: In this article, a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit was proposed for low power digital devices operated at low frequencies, such as RFID, smart cards, and sensors.
Abstract: This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to V dd . It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 ㎒. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

Journal ArticleDOI
05 Oct 2010
TL;DR: The concept of "Logical Stochastic Resonance" (LSR) is reviewed and details of an electronic circuit system demonstrating LSR are provided, including CMOS implementations of a simple LSR circuit, and the concatenation of these LSR modules to emulate combinational logic, such as data flip-flop and full adder operations.
Abstract: In a recent publication it was shown that, when one drives a two-state system with two square waves as input, the response of the system mirrors a logical output (NOR/OR). The probability of obtaining the correct logic response is controlled by the interplay between the noise-floor and the nonlinearity. As one increases the noise intensity, the probability of the output reflecting a NOR/OR operation increases to unity and then decreases. Varying the nonlinearity (or the thresholds) of the system allows one to morph the output into another logic operation (NAND/AND) whose probability displays analogous behavior. Thus, the outcome of the interplay of nonlinearity and noise is a flexible logic gate with enhanced performance. Here we review this concept of "Logical Stochastic Resonance" (LSR) and provide details of an electronic circuit system demonstrating LSR. Our proof-of-principle experiment involves a particularly simple realization of a two-state system realized by two adjustable thresholds. We also review CMOS implementations of a simple LSR circuit, and the concatenation of these LSR modules to emulate combinational logic, such as data flip-flop and full adder operations.

Patent
19 Nov 2010
TL;DR: In this paper, a low-drop out (LDO) regulator circuit is provided having a gate of a pass transistor coupled to an output of an operational transconductance amplifier.
Abstract: A low-drop out (LDO) regulator circuit is provided having a gate of a pass transistor coupled to an output of an operational transconductance amplifier, the LDO regulator exhibiting a non-dominant pole at an output of the LDO. A dynamic zero-compensation circuit is coupled in parallel to the pass transistor. A compensation control circuit is coupled and configured to adjust a frequency, at which a zero is generated, and cause the generated zero to track with the non-dominant pole.

Patent
24 May 2010
TL;DR: In this article, a logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed.
Abstract: A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.

Journal ArticleDOI
TL;DR: A symmetric adiabatic logic is proposed in which the discharge paths are symmetric for data‐independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.
Abstract: We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual-rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data-independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.

Proceedings ArticleDOI
13 Jun 2010
TL;DR: It is shown that the proposed graphene logic has significant advantages over CMOS gate in terms of delay-power product and signal restoration, while maintaining a similar footprint.
Abstract: In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multi-functional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of delay-power product and signal restoration, while maintaining a similar footprint. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing feasible integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.

Journal ArticleDOI
TL;DR: In this article, resonant tunneling diodes (RTDs) with split drain contacts have been realized and the current-voltage characteristics have been studied in the bistable regime at room temperature.
Abstract: Submicron-sized mesas of resonant tunneling diodes (RTDs) with split drain contacts have been realized and the current-voltage characteristics have been studied in the bistable regime at room temperature. Dynamically biased, the RTDs show noise-triggered firing of spikelike signals and can act as reconfigurable universal logic gates for small voltage changes of a few millivolt at the input branches. These observations are interpreted in terms of a stochastic nonlinear processes. The logic gate operation shows gain for the fired-signal bursts with transconductance slopes exceeding the thermal limit. The RTD junction can be easily integrated to arrays of multiple inputs and have thus the potential to mimic neurons in nanoelectronic circuits.

Patent
Jhon Jhy Liaw1
19 Jan 2010
TL;DR: In this paper, the authors define a cell area defined by a first X-pitch and a first Ypitch, the Xpitch being longer than the Y-pitches, and the ratio of the first Y pitch to twice the second logic gate pitch is greater than one.
Abstract: An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is defined by a first X-pitch and a first Y-pitch, the X-pitch being longer than the Y-pitch. A plurality of logic transistors are formed outside of the first SRAM array, the plurality of logic transistors including at least first and second logic transistor having first and second gate pitches defined between their source and drain contacts. The second gate pitch is the minimum logic gate pitch for the plurality of logic transistors. The first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one.

Patent
25 May 2010
TL;DR: In this article, a method and system for modulating logic clock oscillator frequency based on voltage supply is presented, which comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation.
Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Proceedings ArticleDOI
29 Nov 2010
TL;DR: A circuit to accomplish logic operations using MTJs on data that is stored in other MTJs, without an intermediate electronic circuitry is presented, which reduces the performance overheads of the spintronic circuit while also simplifying fabrication.
Abstract: The emerging field of spintronics is undergoing exciting developments with the advances recently seen in spintronic devices, such as magnetic tunnel junctions (MTJs). While they make excellent memory devices, recently they have also been used to accomplish logic functions. The properties of MTJs are greatly different from those of electronic devices like CMOS semiconductors. This makes it challenging to design circuits that can efficiently leverage the spintronic capabilities. The current approaches to achieving logic functionality with MTJs include designing an integrated CMOS and MTJ circuit, where CMOS devices are used for implementing the required intermediate read and write circuitry. The problem with this approach is that such intermediate circuitry adds overheads of area, delay and power consumption to the logic circuit. In this paper, we present a circuit to accomplish logic operations using MTJs on data that is stored in other MTJs, without an intermediate electronic circuitry. This thus reduces the performance overheads of the spintronic circuit while also simplifying fabrication. With this circuit, we discuss the notion of performing logic operations with a non-volatile memory device and compare it with the traditional method of computation with separate logic and memory units. We find that the MTJ-based logic unit has the potential to offer a higher energy-delay efficiency than that of a CMOS-based logic operation on data stored in a separate memory module.

J. Lohstroh1
20 May 2010
TL;DR: ISL is a new 200 mV voltage swing LSI-logic, made in a standard Schottky process, with a better speed, a 10 times lower power dissipation, and a 6 times better packing density than low powerSchottky TTL.
Abstract: Integrated Schottky logic (ISL) is a new 200 mV voltage-swing LSI logic that can be made in standard Schottky processes with a double-layer metallization. It fills the gap between low-power Schottky TTL and I/SUP 2/L for those circuits where low-power Schottky TTL consumes too much power and takes up too much chip area, and when I/SUP 2/L does not attain the required speed. An ISL gate consists of a current source and a set of Schottky output diodes (wired AND gate). Minimum propagation delay times of 2.7 ns at 200 /spl mu/A/gate are obtained, with a speed-power product of 1.2 pJ. The packing density of ISL is 120 to 180 gates/mm/SUP 2/. The logic can be combined with ECL, I/SUP 2/L, and TTL on the same chip, and can also be made in analog processes.

Proceedings ArticleDOI
05 Jul 2010
TL;DR: A set of novel dual rail reversible logic gates for online testable reversible logic design that detects 100% of single faults while reducing the area and the number of garbage outputs up to 6.4X and 4.6X, compared to previously proposed techniques, respectively.
Abstract: Research in reversible logic is motivated by its application in quantum computing as well as its promise in extremely low power consumption by elimination of power dissipation due to information loss. In this paper we propose a set of novel dual rail reversible logic gates for online testable reversible logic design. Experimental results show that our technique detects 100% of single faults while reducing the area and the number of garbage outputs up to 6.4X and 4.6X, compared to previously proposed techniques, respectively.

Journal ArticleDOI
TL;DR: In this paper, a reconfigurable all-optical logic gate for NRZ-PolSK signal based on FWM in a highly nonlinear fiber at 10Gb/s is presented.

Journal ArticleDOI
TL;DR: A simple design philosophy, based on the principles of bipolar electrochemistry, is reported, for the operation of microelectrochemical integrated circuits that could provide on-chip data processing functions for lab-on-a-chip devices.
Abstract: Here we report a simple design philosophy, based on the principles of bipolar electrochemistry, for the operation of microelectrochemical integrated circuits. The inputs for these systems are simple voltage sources, but because they do not require much power they could be activated by chemical or biological reactions. Device output is an optical signal arising from electrogenerated chemiluminescence. Individual microelectrochemical logic gates are described first, and then multiple logic circuits are integrated into a single microfluidic channel to yield an integrated circuit that can perform parallel logic functions. AND, OR, NOR, and NAND gates are described. Eventually, systems such as those described here could provide on-chip data processing functions for lab-on-a-chip devices.

Patent
30 Apr 2010
TL;DR: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL) was proposed in this paper, which provides delay-insensitive logic operation with significant leakage power and active energy reduction.
Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL) The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead

Journal ArticleDOI
25 Mar 2010
TL;DR: This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL), and proposes quaternary multiplier circuit to achieve required optimization.
Abstract: This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL) Quaternary to binary and binary to quaternary converters are designed using down literal circuits Negation in modular arithmetic is designed with only one gate Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration Quaternary multiplier circuit is proposed to achieve required optimization Simulation result of each operation is shown separately using Hspice

Journal ArticleDOI
TL;DR: An experimental proof of principle for a ternary multiplier realized in terms of the charge state of a single dopant atom embedded in a fin field effect transistor (Fin-FET).
Abstract: We provide an experimental proof of principle for a ternary multiplier realized in terms of the charge state of a single dopant atom embedded in a fin field effect transistor (Fin-FET). Robust reading of the logic output is made possible by using two channels to measure the current flowing through the device and the transconductance. A read out procedure that allows for voltage gain is proposed. Long numbers can be multiplied by addressing a sequence of Fin-FET transistors in a row.

Journal ArticleDOI
TL;DR: This minireview focuses on all-photonic molecular logic gates, in which light is used as an input signal for transferring the system from one state to another and for reading the output signal by absorption or luminescence.
Abstract: The possibility of performing logical operations at the molecular level is being actively investigated at present with the aim of developing molecular logic gates, which can be used in information technologies In this minireview, the design algorithm of molecular logic gates is considered and the requirements on molecular systems for use as logic gates are specified Examples of molecular logic gates performing different logical operations are given Attention is focused on all-photonic molecular logic gates, in which light is used as an input signal for transferring the system from one state to another and for reading the output signal by absorption or luminescence In addition, optoelectronic devices with light as the input signal and electric current as the output signal are briefly discussed

Proceedings ArticleDOI
16 Aug 2010
TL;DR: In this article, a Differential Cascode Voltage-Switch Logic (DCVSL)-like design is applied to the design of arbitrary NULL Convention Logic (NCL) gates, which have hysteresis state holding capability.
Abstract: This paper demonstrates the performance, area and supply voltage scaling advantages of a Differential Cascode Voltage-Switch Logic (DCVSL)-like design over previous methods for designing C-elements. The DCVSL-like method is then applied to the design of arbitrary NULL Convention Logic (NCL) gates, which have hysteresis state-holding capability.