Showing papers on "Pass transistor logic published in 2012"

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

Abstract: A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.

MRL — Memristor Ratioed Logic

Abstract: Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) — a hybrid CMOS-memristive logic family — is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are added to provide a complete logic structure and signal restoration. Unlike previously published memristive-based logic families, the MRL family is compatible with standard CMOS logic. A case study of an eight-bit full adder is presented and related design considerations are discussed.

Logic encryption: a fault analysis perspective

Abstract: The globalization of Integrated Circuit (IC) design flow is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware trojans; the IC industry is losing approximately $4 billion annually [1], [2]. One way to protect the ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design [3] and does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis based logic encryption technique. This technique achieves 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved by using a smaller number of additional gates when compared to random logic encryption.

CMOS-based carbon nanotube pass-transistor logic integrated circuits.

Abstract: Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

Design of a Ternary Memory Cell Using CNTFETs

Abstract: This paper presents a novel design of a ternary memory cell using carbon nanotube field-effect transistors (CNTFETs). Ternary logic is a promising alternative to conventional binary logic because it allows simplicity and energy efficiency in modern digital design due to the reduced circuit overhead in interconnects and chip area. In this paper, a novel design of a ternary memory cell based on CNTFETs is proposed; this cell uses a transmission gate for the write operation and a buffer for the read operation to make them separate. Chirality of the CNTFETs is utilized for threshold voltage control, thus avoiding the use of additional power supplies. Extensive simulation results using SPICE are reported to show that the two memory operations of the proposed ternary cell perform correctly at 0.9 V power supply. The static noise margin and read/write delay of the proposed ternary memory cell are also very good; by utilizing the latest CNTFET layout design tools, it is shown that the proposed ternary memory cell achieves a significant saving in area (41.6%) compared with its CMOS ternary counterpart at 32 nm.

Low Energy Magnetic Domain Wall Logic in Short, Narrow, Ferromagnetic Wires

Abstract: We present circuit simulation results of an implementation of universal logic that operates at low switching energy. Information is stored in the position of a single domain wall in a thin, short ferromagnetic wire. The gate is switched by current-driven domain wall motion, and information is read out using a magnetic tunnel junction. The inputs and outputs of the device are currents controlled by voltage clocks, making it compatible with CMOS. Using devices that operate at 100-1 mV, we simulate a shift register circuit and a full-adder circuit. The simulations show that the magnetic logic gates can operate at lower switching energy than CMOS electronics.

High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process

Abstract: A new high density Contact RRAM (CRRAM) cell realized in pure high-k metal gate 28nm CMOS logic process with a very small 35nm×35nm resistive contact hole has been fabricated without extra masking or process step. This study reports the first time of a manufacturable tiny resistive node of RRAM cell on a 28nm CMOS logic platform and fully compatible with high-k metal gate processes. The 28nm Contact RRAM cell exhibits a stable operation window with a very small cell size of 0.03μm2. Due to the scale down and uniform manufacturing process, the cell reliably operates in a low set voltage of 3V and an acceptable reset current of 60μA/cell with short set and reset time of 500ns and 100us. Excellent endurance of more than 1M cycles and stable data retention at high temperature further support the 28nm Contact RRAM will be a promising SOC memory in the future.

DNA computation: a photochemically controlled AND gate.

Abstract: DNA computation is an emerging field that enables the assembly of complex circuits based on defined DNA logic gates. DNA-based logic gates have previously been operated through purely chemical means, controlling logic operations through DNA strands or other biomolecules. Although gates can operate through this manner, it limits temporal and spatial control of DNA-based logic operations. A photochemically controlled AND gate was developed through the incorporation of caged thymidine nucleotides into a DNA-based logic gate. By using light as the logic inputs, both spatial control and temporal control were achieved. In addition, design rules for light-regulated DNA logic gates were derived. A step-response, which can be found in a controller, was demonstrated. Photochemical inputs close the gap between DNA computation and silicon-based electrical circuitry, since light waves can be directly converted into electrical output signals and vice versa. This connection is important for the further development of an...

An Energy-Efficient Memristive Threshold Logic Circuit

Abstract: Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.

mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices

Abstract: This paper introduces the design of logic circuits based exclusively on novel magnetoelectronic devices. Current signals are steered by 2× resistance change switching while operating with sub-100 mV voltage pulses for power and synchronization. The inherent memory of the devices results in fully pipelined nonvolatile logic. We demonstrate that co-optimization of the devices, circuits and logic can achieve ultra-low energy-per-operation for design examples.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography

Abstract: Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Uniform methodology for benchmarking beyond-CMOS logic devices

Abstract: A consistent methodology for benchmarking beyond CMOS logic devices was developed to guide the research directions. The promising devices — tunneling FET and spin wave devices — perform > 1015 Integer Ops/s/cm2 with power < 1W/cm2.

Magnetic Tunnel Junction-Based Spintronic Logic Units Operated by Spin Transfer Torque

Abstract: Magnetic tunneling junction (MTJ)-based programmable logic devices have been proposed and studied for future reconfigurable and nonvolatile computation devices and systems. Spin transfer torque (STT)-based switching has advantages in device scaling compared to the field-switching mechanism. However, the previously proposed MTJ logic devices have operated independently and, therefore, are limited to only basic logic operations. Consequently, the MTJ device has only been used as an ancillary device, rather than the main computation device. As a result, the full benefits of MTJ-based computation have not been explored. New designs are needed to accelerate the development of the MTJ-based logic devices. Specifically the realization of direct communication between the MTJ devices is crucial to fully utilize the MTJ devices in the circuits to implement more advanced logic functions. In this paper, new MTJ-based spintronic logic units (building blocks) for spintronic circuits using the STT switching mechanism have been proposed and investigated, which includes the designs of a basic STT-MTJ logic cell, a direct communication between the MTJ logic cells, a three-MTJ logic unit and a spintronic logic circuit acting as an arithmetic logic unit.

An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC

Abstract: This paper presents an output-capacitor-free adaptively biased low-dropout regulator with subthreshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of adaptive biasing (AB) and Miller compensation with Q-reduction are employed to achieve low-voltage high-precision regulation with extended loop bandwidth while maintaining low quiescent current and high current efficiency. The pass transistor is designed to work in the linear region at heavy load to save silicon area, and a symmetrically matched current-voltage mirror is used to implement the AB scheme with accurate current sensing for the full load range. The dedicated STUR circuit, which is low-voltage compatible and consumes very low current in the steady state, is inserted to momentarily but exponentially increase the gate discharging current of the pass transistor when the LDR output has a large undershoot due to a large step up of the load current. Undershoot voltage is hence dramatically reduced. Stability of the ABSTUR LDR is thoroughly analyzed and tradeoffs between the undershoot-reduction strength and the light load stability are discussed. Features of the proposed ABSTUR LDR are experimentally verified by a prototype fabricated in a standard 0.35-μm CMOS process.

Simple and universal platform for logic gate operations based on molecular beacon probes.

Abstract: A new platform technology is herein described with which to construct molecular logic gates by employing the hairpin-structured molecular beacon probe as a basic work unit. In this logic gate operation system, single-stranded DNA is used as the input to induce a conformational change in a molecular beacon probe through a sequence-specific interaction. The fluorescent signal resulting from the opening of the molecular beacon probe is then used as the output readout. Importantly, because the logic gates are based on DNA, thus permitting input/output homogeneity to be preserved, their wiring into multi-level circuits can be achieved by combining separately operated logic gates or by designing the DNA output of one gate as the input to the other. With this novel strategy, a complete set of two-input logic gates is successfully constructed at the molecular level, including OR, AND, XOR, INHIBIT, NOR, NAND, XNOR, and IMPLICATION. The logic gates developed herein can be reversibly operated to perform the set-reset function by applying an additional input or a removal strand. Together, these results introduce a new platform technology for logic gate operation that enables the higher-order circuits required for complex communication between various computational elements.

Demonstration of reconfigurable electro-optical logic with silicon photonic integrated circuits

Abstract: We demonstrate a scalable and reconfigurable optical directed-logic architecture consisting of a regular array of integrated optical switches based on microring resonators. The switches are controlled by electrical input logic signals through embedded p-i-n junctions. The circuit can be reconfigured to perform any combinational logic operation by thermally tuning the operation modes of the switches. Here we show experimentally a directed logic circuit based on a 2×2 array of switches. The circuit is reconfigured to perform arbitrary two-input logic functions.

Cascading wafer-scale integrated graphene complementary inverters under ambient conditions.

Abstract: The fundamental building blocks of digital electronics are logic gates which must be capable of cascading such that more complex logic functions can be realized. Here we demonstrate integrated graphene complementary inverters which operate with the same input and output voltage logic levels, thus allowing cascading. We obtain signal matching under ambient conditions with inverters fabricated from wafer-scale graphene grown by chemical vapor deposition (CVD). Monolayer graphene was incorporated in self-aligned field-effect transistors in which the top gate overlaps with the source and drain contacts. This results in full-channel gating and leads to the highest low-frequency voltage gain reported so far in top-gated CVD graphene devices operating in air ambient, Av ∼ −5. Such gain enabled logic inverters with the same voltage swing of 0.56 V at their input and output. Graphene inverters could find their way in realistic applications where high-speed operation is desired but power dissipation is not a concer...

Novel STT-MTJ Device Enabling All-Metallic Logic Circuits

Abstract: Spintronics is an emerging platform for logic circuit design. Though many approaches have been proposed, and several have met with some success, a number of challenges remain. Here, we introduce a new style of magnetic logic-mLogic-enabled by a novel four-terminal device. An input current pulse to the device switches the magnetic state by spin transfer torque-driven domain wall motion, which programs the resistance state of a magnetic tunnel junction in an electrically-insulated but magnetically-coupled path. Despite the low switching ratios of the devices, limited by the tunnel magnetoresistance ratio, logic circuits independent of CMOS may be configured using current-based signaling. Micromagnetic analysis of device performance and the concepts of mLogic circuit design are introduced, with SPICE simulation of logic gates demonstrating correct logic operation at supplies below 100 mV.

Uncle - An RTL Approach to Asynchronous Design

Abstract: Uncle (Unified NULL Convention Logic Environment) is an end-to-end toolset for creating asynchronous designs using NULL Convention Logic (NCL). Designs are specified in Verilog RTL, with the user responsible for specifying registers, data path elements, and finite state machines for controlling data path sequencing. A commercial synthesis tool is used to produce a gate-level net list of primitive logic gates and storage elements, which is then transformed into an NCL net list by the Uncle mapping flow. Performance optimizations supported by the flow are net buffering for target slew and delay balancing between latch stages. Both data-driven and control-driven (i.e. Balsa-style) schemes are supported. Transistor count, performance, and energy comparisons are made for Uncle versus Balsa-generated net lists for GCD and Viterbi decoder designs, with the Uncle designs comparing favorably in all three areas.

On modeling faults in FinFET logic circuits

Abstract: FinFET transistor has much better short-channel characteristics than traditional planar CMOS transistor and will be widely used in next generation technology. Due to its significant structural difference from conventional planar devices, it is essential to revisit whether existing fault models are applicable to detect faults in FinFET logic gates. In this paper, we study some unique defects in FinFET logic circuits and simulate their faulty behavior. Our simulation study shows that most of the defects can be covered with existing fault models, but they vary under different cases and test strategies may need to be augmented to target them.

A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates

Abstract: In this paper, a simple approach to reduce delay variations in domino logic gates is proposed. Previous analysis by the same authors showed that delay variations in domino logic are mainly due to the feedback loop implemented by the keeper transistor and the output inverter gate. Accordingly, the proposed strategy aims at reducing the loop gain associated with this feedback loop, and hence its impact on delay variations. In particular, a simple modified keeper is proposed to reduce the loop gain while keeping the same silicon area, noise margin, and nominal performance. The resulting delay variations associated with keeper insertion are shown to be lowered by approximately 50%. The proposed approach is assessed by means of simulations in 65-nm and 90-nm commercial CMOS technologies.

Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance

Abstract: This paper presents the design and characterization of 12 full-adder circuits in the IBM 90-nm process. These include three new full-adder circuits using the recently proposed split-path data driven dynamic logic. Based on the logic function realized, the adders were characterized for performance and power consumption when operated under various supply voltages and fan-out loads. The adders were then further deployed in a 32 bit ripple carry adder and 8×4 multiplier to evaluate the impact of sum and carry propagation delays on the performance, power of these systems. Performance characterization of the adder circuits in the presence of process and voltage variations was also performed through Monte Carlo simulations. Besides analyzing and comparing circuit performance, the possible impact of the choice of logic function has also been underlined in this study.

New Methodology for the Design of Efficient Binary Addition Circuits in QCA

Abstract: The quantum-dot cellular automata (QCA) approach is an attractive emerging technology suitable for the development of ultradense low-power high-performance digital circuits. Even though several solutions have been proposed recently for binary addition circuits, the design of efficient adders in QCA still poses several challenges since, most often, designers tend to implement strategies and methodologies close to those consolidated for the CMOS logic design. In this paper, we propose a new design method that exploits in original ways the properties of auxiliary propagate and generates signals to reduce the number of majority gates required to implement adders in QCA and/or the addition time. Three new formulations of basic logic equations frequently used in the designs of fast binary adders are proposed. To evaluate the potential advantage of the new strategy, two examples of application of the aforementioned method are discussed in this paper.

Nonvolatile memory device and method of driving the same

Abstract: A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.

Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture

Abstract: Dipolar magnetic coupling between single layer nanomagnets is used in nanomagnetic logic (NML). Apart from writing and reading, nanomagnets are also clocked using external magnetic fields generated by current carrying wires. The related current ranges in mA and consumes large power. Also, the fields cannot sharply terminate at boundaries between nanomagnets that are required to be in different clock zones. The above concerns motivated us to look into alternate magnetic devices to realize magnetic logic. We therefore suggested miltilayer magnetic tunnel junctions (MTJs) for logic. We have observed that MTJ free layers can interact with their neighbors through magnetic coupling. In this paper we have proposed use of this coupling for effective logic computation. MTJs are also CMOS friendly, a property that we used to write, clock and read from logic. CMOS integration also improves control over individual elements in logic. In this paper we have used these properties to present a novel CMOS-MTJ integrated architecture that: a) computes logic using magnetic coupling between MTJs and b) writes, clocks and reads from logic using spin transfer torque (STT) current that is more energy efficient. A feasibility study of this CMOS-MTJ integration in 22 nm CMOS technology node is also presented. The proposed architecture achieves an energy reduction >;95% in adders and multipliers when compared to traditional designs using single layer nanomagnets.

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates

Abstract: Reversible logic has promising applications in dissipation less optical computing, low power computing, quantum computing etc. Reversible circuits do not lose information, and there is a one to one mapping between the input and the output vectors. In recent years researchers have implemented reversible logic gates in optical domain as it provides high speed and low energy computations. The reversible gates can be easily fabricated at the chip level using optical computing. The all optical implementation of reversible logic gates are based on semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI). The Mach-Zehnder interferometer has advantages such as high speed, low power, easy fabrication and fast switching time. In the existing literature, the NAND logic based implementation is the only implementation available for reversible gates and functions. There is a lack of research in the direction of NOR logic based implementation of reversible gates and functions. In this work, we propose the NOR logic based all optical reversible gates referred as all optical TNOR gate and all optical PNOR gate. The proposed all optical reversible NOR logic gates can implement the reversible boolean logic functions with reduced optical cost and propagation delay compared to their implementation using existing all optical reversible NAND gates. The advantages in terms of optical cost and delay is illustrated by implementing 13 standard boolean functions that can represent all 256 possible combinations of three variable boolean function.

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements

Abstract: This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high- k/metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy.

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.