Showing papers on "Pass transistor logic published in 2015"

Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits

Abstract: A new benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, straintronic, and orbitronic computational state variables. Standby power treatment and memory circuits are included. The set of circuits is extended to sequential logic, including arithmetic logic units. The conclusion that tunneling field-effect transistors are the leading low-power option is reinforced. Ferroelectric transistors may present an attractive option with faster switching delay. Magnetoelectric effects are more energy efficient than spin transfer torque, but the switching speed of magnetization is a limitation. This article enables a better focus on promising beyond-CMOS exploratory devices.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Abstract: In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors

Abstract: Reconfigurable silicon nanowire field-effect transistors (RFETs) combine the functionality of classical unipolar p-type and n-type FETs in one universal device. In this paper, we show devices exhibiting full symmetry between p- and n-functionality, while having identical geometry. Scaling trends and feasibility for digital circuit integration are evaluated based on TCAD simulations. The method of logical effort is applied to analyze fundamental differences in circuit topology using this unique type of multigate transistors. We introduce a set of multifunctional logic gates based on RFETs providing all basic Boolean functions, including nand / nor , and / or, and xor/xnor, and compared them with classical implementations. Two 1-bit full adders based on those gates are presented as an insightful example that RFETs are one possible solution to increase the system functionality. Moreover, it is shown that an asymmetric transistor layout with individual optimization of both top gates can be used to increase the speed of those circuits.

Fast boolean logic mapped on memristor crossbar

Abstract: As the CMOS technology is gradually scaling down to inherent physical device limits, significant challenges emerge related to scalability, leakage, reliability, etc. Alternative technologies are under research for next-generation VLSI circuits. Memristor is one of the promising candidates due to its scalability, practically zero leakage, non-volatility, etc. This paper proposes a novel design methodology for logic circuits targeting memristor crossbars. This methodology allows the optimization of the design of logic function, and their automatic mapping on the memristor crossbar. More important, this methodology supports the execution of Boolean logic functions within constant number of steps independent of its functionality. To illustrate the potential of the proposed methodology, multi-bit adders and multipliers are explored; their incurred delay, area and energy costs are analyzed. The comparison of our approach with state-of-the-art Boolean logic circuits for memristor crossbar architecture shows significant improvement in both delay (4 to 500 x) and energy consumption (1.22 to 3.71 x). The area overhead may decrease (down to 44%) or increase (up to 17%) depending on the circuit's functionality and logic optimization level.

Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch

Abstract: The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods—in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits—are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage.

Normally-off Logic Based on Resistive Switches—Part I: Logic Gates

Abstract: To extend the scaling of digital integrated circuits, beyond-CMOS approaches based on advanced materials and novel switching concepts are strongly needed. Among these approaches, the resistive switching random access memory (RRAM) allows for fast and nonvolatile switching at scalable power consumption. This work presents functionally complete logic gates based on RRAM technology. Logic computation is obtained through conditional switching in RRAM circuits with serially connected switches. AND, implication, NOT, and bit transfer operations are demonstrated, each using a single clock pulse, while other functions (e.g., OR and XOR) are achieved in multiple steps. The results support RRAM logic for normally-off digital circuits with extremely high density.

Verification of gate-level arithmetic circuits by function extraction

Abstract: The paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed by the circuit directly from its gate-level implementation. The method can be used to verify the arithmetic function computed by the circuit against its known specification, or to extract the arithmetic function implemented by the circuit. Experiments were performed on arithmetic circuits synthesized and mapped onto standard cells using ABC system. The results demonstrate scalability of the method to large arithmetic circuits, such as multipliers, multiply-accumulate, and other elements of arithmetic datapaths with up to 512-bit operands and over 2 Million gates. The procedure has linear runtime and memory complexity, measured by the number of logic gates.

DNA-based visual majority logic gate with one-vote veto function

Abstract: A molecular logic gate is a basic element and plays a key role in molecular computing. Herein, we have developed a label-free and enzyme-free three-input visual majority logic gate which is realized for the first time according to DNA hybridization only, without DNA replacement and enzyme catalysis. Furthermore, a one-vote veto function was integrated into the DNA-based majority logic gate, in which one input has priority over other inputs. The developed system can also implement multiple basic and cascade logic gates.

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes

Abstract: Low-power mobile devices such as RFID tags and WSNs that employ AES cryptographic modules are susceptible to differential power analysis (DPA) attacks. This paper presents a novel secured quasi-adiabatic logic (SQAL) technology that is both low-power and DPA immune. The efficiency of the SQAL technology was evaluated on an 8-bit AES-128 SBOX block and proved to be robust against DPA attacks. Compared to other adiabatic and non-adiabatic logic styles, the SQAL technology achieves better results in terms of power consumption and area overhead.

16 Boolean logics in three steps with two anti-serially connected memristors

Abstract: Memristor based logic gates that can execute memory and logic operations are regarded as building blocks for non Von Neumann computation architecture. In this letter, Ta/GeTe/Ag memristors were fabricated and showed reproducible binary switches between high-resistance and low-resistance states. Utilizing a structure with two anti-serially connected memristors, we propose a logic operation methodology, based on which arbitrary Boolean logic can be realized in three steps, and the logic result can be nonvolatilely stored. A functionally complete logic operation: NAND is further verified by HSPICE simulation and experiments. The implementation of logic-in-memory unit may stimulate the development of future massive parallel computing.

A Novel Design for Memristor-Based Logic Switch and Crossbar Circuits

Abstract: Recently, it has been demonstrated that memristors can be utilized as logic gates, control switches as well as memory elements. In this paper, we analyze the different AND, OR, and NOT logic gates which are based on memristors. In addition, a novel design for a memristor-based switch is presented, which can be used in the peripheral read/write circuits of the memristor-based memory. Moreover, methods of consecutive read with long refresh intervals and fast write for the proposed design are also discussed. Another highlight of this work is the analysis of the proposed memristor-based crossbar architecture which has a series of excellent features, such as good-compatibility, high-density, non-volatility, low-power, and good-scalability. Simulation results also show that the proposed memory array has superior performances compared to other memristor-based arrays proposed in the existing technical literature.

The Bootstrapped Switch [A Circuit for All Seasons]

Abstract: Field-effect transistors (FETs) have been used as switches, particularly for analog signals, since the 1950s. In the early days of analog sampling, it was discovered that such devices exhibit an input-dependent on-resistance, thereby introducing distortion. This issue can be resolved by ?bootstrapping,? a circuit technique that minimizes the switch on-resistance variation in the presence of large input and output voltage swings. In this article, we study the bootstrapped switch topology and appreciate its role in nanometer designs.

Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction

Abstract: With the continuous shrinking of technology node, conventional CMOS logic circuits suffer from high power issues due to both increasing leakage current and long traffic delay. Hybrid non-volatile (NV) logic-in-memory architecture, where emerging NV memories are distributed over a logic-circuit plane, has been widely investigated to overcome these limitations. Magnetic tunnel junction (MTJ) is considered as one of the most promising NV candidates thanks to its non-volatility, fast access speed, infinite endurance and easy 3-D integration with CMOS technology. Recently, several 1-bit NV full-adder (FA) structures using MTJ have been proposed to build low-power high-density arithmetic/logic unit for processors. However, one of their major disadvantages is partial non-volatility since they only use MTJs as one of their operands. For the purpose of extending 1-bit NV-FA to multi-bit structure and realizing full non-volatility, synchronous 8-bit NV-FA architecture is presented in this paper, where all the input signals are stored in MTJs instead of CMOS registers. Three possible structures are proposed with respect to different locations of NV data. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validated their functionalities and compared their performances in terms of power consumption and area, etc.

Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Abstract: Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.

Vertical device architecture for 5nm and beyond: Device & circuit implications

Abstract: Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.

Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications

Abstract: In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies.

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

Abstract: Side-channel attacks are one of the major concerns for security-enabled applications as they make use of information leaked by the physical implementation of the underlying cryptographic algorithm. Hence, reducing the side-channel leakage of the circuits realizing the cryptographic primitives is amongst the main goals of circuit designers. In this paper, we present a novel circuit concept, which decouples the main power supply from an internal power supply that is used to drive a single logic gate. The decoupling is done with the help of buffering capacitances integrated into semiconductor. We also introduce—compared to the previously known schemes—an improved decoupling circuit which reduces the crosstalk from the internal to the external power supply. The result of practical side-channel evaluation on a prototype chip fabricated in a 150nm CMOS technology shows a high potential of our proposed technique to reduce the side-channel leakages.

Memristive Threshold Logic Circuit Design of Fast Moving Object Detection

Abstract: Real-time detection of moving objects involves memorization of features in the template image and their comparison with those in the test image. At high sampling rates, such techniques face the problems of high algorithmic complexity and component delays. We present a new resistive switching-based threshold logic cell which encodes the pixels of a template image. The cell comprises a voltage divider circuit that programs the resistances of the memristors arranged in a single-node threshold logic network, and the output is encoded as a binary value by using a CMOS inverter gate. When a test image is applied to the template-programmed cell, a mismatch in the respective pixels is seen as a change in the output voltage of the cell. The proposed cell when compared with CMOS equivalent implementation shows improved performance in area, leakage power, power dissipation, and delay.

Randomized Multitopology Logic Against Differential Power Analysis

Abstract: Side channel attacks have become one of the most significant problems in modern digital systems. In particular, differential power analysis (DPA) has emerged as a powerful technique because it does not require any assumptions regarding the hardware implementation of a crypto-chip. In this paper, a new randomized multitopology logic (RMTL) is proposed to enhance immunity to DPA. RMTL refers to a family of dedicated security-oriented gates whose power profile cannot be predicted by external observers. Specifically, each gate of this logic can be configured in real time to operate in a different circuit topology, where each topology induces a different power profile. Immunity to DPA attacks is obtained by randomly changing each gate’s topology on run time. The suggested approach can coexist with common existing countermeasures. Theoretical analysis and simulation results, conducted in a standard 40-nm technology, clearly show higher immunity to DPA attacks when using the proposed approach compared with standard CMOS implementation.

A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines

Abstract: Recent works in the synthesis of reversible logic circuits have been motivated by ever increasing emphasis on low-power design alternatives, and recent developments in quantum computing. Although most of the synthesis approaches use multiple-control Toffoli (MCT) gates with positive control lines, a few recent works have also considered MCT gates with negative control lines resulting in better circuit realizations. Some of the works have also tried to carry out post-synthesis optimization of given MCT gate netlists with positive control lines, using template matching and similar netlist transformation techniques. However, only one work is reported that attempts to optimize netlists containing negative control MCT gates. This paper proposes an efficient optimization technique for MCT gate netlists with both positive and negative control lines, which is based on repeated applications of a small set of pairwise gate merging and replacement rules. Experiments carried out on reversible circuit benchmarks show that it is possible to achieve significant reductions in number of gates and quantum costs.

1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks

Abstract: A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential Power Analysis (DPA) attacks. Based on measurements, the AES core achieves a throughput of 16.90Gbps and power consumption of 98mW, exhibiting 720x higher DPA resistance and 30% lower power than its conventional CMOS counterpart at the same clock frequency.

A Novel Design for a Memristor-Based or Gate

Abstract: This brief proposes a logic gate that performs a stateful or logic operation on memristor memory. The presented logic structure concurrently executes an or operation in the nanocrossbar architecture in a single step, which enables a fast logic operation and reduces the number of required memristors. The proposed circuit completes the in situ logic operation on the memristor memory, which alleviates the burden of the processor significantly. Through analysis and simulation, the feasibility of the or operation is demonstrated, and the parameter optimization is analyzed.

Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication

Abstract: Brain-inspired circuits can provide an alternative solution to implement computing architectures taking advantage of fault tolerance and generalization ability of logic gates. In this brief, we advance over the memristive threshold circuit configuration consisting of memristive averaging circuit in combination with operational amplifier and/or CMOS inverters in application to realizing complex computing circuits. The developed memristive threshold logic gates are used for designing fast Fourier transform and multiplication circuits useful for modern microprocessors. Overall, the proposed threshold logic outperforms previous memristive-CMOS logic cells on every aspect, however, they indicate a lower chip area, lower total harmonic distortion, and controllable leakage power, but a higher power dissipation with respect to CMOS logic.

Synthesis of Majority/Minority Logic Networks

Abstract: As CMOS technology reaches its physical limits, new technologies such as quantum-dot cellular automata, single electron tunneling, and tunneling-phase logic are being proposed as alternatives to CMOS technology. These technologies use either majority or minority logic to implement logic functions. Existing majority/minority logic synthesis methods, based on three-feasible networks, often result in suboptimal solutions. In this paper, an efficient algorithm to find the minimal majority gate mapping, along with a majority expression look-up table (MLUT) is developed. Based on the MLUT, a comprehensive majority/minority logic synthesis technique is proposed. A redundancy removal method is also developed to further optimize the synthesized circuit. This technique makes effort toward achieving different optimization goals and results in fewer majority gates and fewer levels than previous methods. For the 29 MCNC benchmark circuits, when targeted to optimize the logic levels, there is an average reduction of 7.0% in the number of levels as well as 6.3% in the number of gates. For optimization targeted to reduce gate counts, there is an average reduction of 9.5% in the number of gates as well as 0.8% in the number of levels, as compared to the best available method.

Hybrid Memristor-CMOS (MeMOS) based Logic Gates and Adder Circuits

Abstract: Practical memristor came into picture just few years back and instantly became the topic of interest for researchers and scientists. Memristor is the fourth basic two-terminal passive circuit element apart from well known resistor, capacitor and inductor. Recently, memristor based architectures has been proposed by many researchers. In this paper, we have designed a hybrid Memristor-CMOS (MeMOS) logic based adder circuit that can be used in numerous logic computational architectures. We have also analyzed the transient response of logic gates designed using MeMOS logic circuits. MeMOS use CMOS 180 nm process with memristor to compute boolean logic operations. Various parameters including speed, ares, delay and power dissipation are computed and compared with standard CMOS 180 nm logic design. The proposed logic shows better area utilization and excellent results from existing CMOS logic circuits at standard 1.8 V operating voltage.

Implementation of circuit in different adiabatic logic

Abstract: Adiabatic circuits are widely employed in Low power VLSI circuit to achieve power efficient system at the cost of reduced performance. The power saving of adiabatic circuit can reach more than 90% compared to conventional static CMOS logic for extreme low frequency applications. The power efficiency of 4:1 multiplexer, designed in different adiabatic logic families is presented in this paper. Power saving more than 50% is achievable beyond 1000MHz also.

Giant spin hall effect (GSHE) logic design for low power application

Abstract: Conventional CMOS transistors will reach its power wall, a huge leakage power consumption limits the performance growth when technology scales down, especially beyond 45nm technology nodes. Spin based devices are one of the alternative computing technologies that aims to replace the current MOS based circuits by taking the advantage of their attractive characteristics, including non-volatility, high integration density and small cell area. The development of technologies such as spin-transfer torque random access memory (STT-RAM) and spin torque majority gate logic has become a story of great success. However, most of these technologies faces problems like, small operation margin, poor fan-out ability, etc. As the latest spin technology, Giant Spin Hall Effect (GSHE) Magnetic Tunneling Junction (MTJ) demonstrates a much better operation speed, switching probability and resistance margin. By leveraging the benefit of greater power efficiency and area density, GSHE MTJ elements become a suitable candidate for spintronic logic gates. Compare with traditional MOS transistors based logic gates, GSHE MTJ based logic can operate as a non-volatile memory and requires a much smaller number of elements to perform same logical operations (i.e., 'AND', 'OR', 'NAND' or 'NOR' gate.). And compare with other spin based logics, GSHE MTJ based logic also provides an better performance, excellent CMOS process compatibility and great fan-out ability.

Normally-off Logic Based on Resistive Switches—Part II: Logic Circuits

Abstract: Logic gates based on the resistive switching random access memory (RRAM) allow normally-off digital computing because of the nonvolatile nature of the RRAM switch [1] . An extremely small area consumption can be achieved because of the 2–terminal structure of the RRAM switch and its capability of 3-D stacking. However, the details of RRAM organization within the array must be thoroughly investigated. This paper discusses the array organization and the select/unselect schemes of the RRAM logic circuits. We demonstrate a 1-bit adder to support the high functionality of RRAM logic. These results support RRAM as a promising technology for nonvolatile logic circuits beyond CMOS.

Design of Schmitt Trigger Logic Gates Using DTMOS for Enhanced Electromagnetic Immunity of Subthreshold Circuits

Abstract: This paper presents subthreshold digital circuit design and optimization method using Schmitt trigger logic gates for enhanced electromagnetic immunity. The proposed Schmitt trigger logic gates are based on a buffer design using dynamic threshold-voltage MOS for low-power operation. By expanding the Schmitt trigger to NAND/NOR gate, we can dramatically improve the noise immunity with much lower switching power consumption and significant area reduction compared with CMOS Schmitt triggers, at the expense of a slight increase in delay. Not only for the gate level, but also the circuit level immunity improvement is verified with ISCAS 85 benchmark. In addition, we propose a parameter to determine the optimal noise immunity considering the tradeoff between immunity and performance. By using the proposed parameter, optimal hysteresis can be chosen for the reasonable performance deterioration.