Showing papers on "Pass transistor logic published in 2016"

Microelectromechanical reprogrammable logic device.

Abstract: In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

Reliability-aware design to suppress aging

Abstract: Due to aging, circuit reliability has become extraordinary challenging. Reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this paper, we propose to bring aging awareness to EDA tool flows based on so-called degradation-aware cell libraries. These libraries include detailed delay information of gates/cells under the impact that aging has on both threshold voltage (V th ) and carrier mobility (μ) of transistors. This is unlike state of the art which considers V th only. We show how ignoring s degradation leads to underestimating guard-bands by 19% on average. Our investigation revealed that the impact of aging is strongly dependent on the operating conditions of gates (i.e. input signal slew and output load capacitance), and not solely on the duty cycle of transistors. Neglecting this fact results in employing insufficient guard-bands and thus not sustaining reliability during lifetime. We demonstrate that degradation-aware libraries and tool flows are indispensable for not only accurately estimating guardbands, but also efficiently containing them. By considering aging degradations during logic synthesis, significantly more resilient circuits can be obtained. We further quantify the impact of aging on the degradation of image processing circuits. This goes far beyond investigating aging with respect to path delays solely. We show that in a standard design without any guardbanding, aging leads to unacceptable image quality after just one year. By contrast, if the synthesis tool is provided with the degradation-aware cell library, high image quality is sustained for 10 years (even under worst-case aging and without a guardband). Hence, using our approach, aging can be effectively suppressed.

Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls.

Abstract: Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. Ferromagnetic nanowires act as conduits for magnetic domain walls which may in principle be used to encode and propagate information. Here, the authors present current-based nanowire domain wall logic prototypes with operational properties required for real devices.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks

Abstract: We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal−oxide−semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows t...

A RET-supported logic gate combinatorial library to enable modeling and implementation of intelligent logic functions

Abstract: Boolean logic gates integrate multiple digital inputs into a digital output. Among these, logic gates based on nucleic acids have attracted a great deal of attention due to the prospect of controlling living systems in the way we control electronic computers. Herein, by employing Thioflavin T (ThT) as a signal transducer, we integrated multiple components based on RET (a type of proto-oncogene) into a logic gate combinatorial library, including basic logic gates (NOR, INHIBIT, IMPLICATION), a single three-input NOR gate, and combinatorial gates (INHIBIT–OR, NOT–AND–NOR). In this library, gates were connected in series where the output of the previous gate was the input for the next gate. Subsequently, by taking advantage of the library, some intelligent logic functions were realized. Expectedly, a biocomputing keypad-lock security system was designed by sequential logic operations. Moreover, a parity checker which can identify even numbers and odd numbers from natural numbers was established successfully. This work helps elucidate the design rules by which simple logic can be harnessed to produce diverse and complex calculations by rewiring communication between different gates. Together, our system may serve as a promising proof of principle that demonstrates increased computational complexity by linking multiple logic gates together.

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs

Abstract: Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed Majority-Inverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMP-based realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing—particularly in MAJ-based realizations—and the use of techniques proposed for optimization.

Optimized stateful material implication logic for three-dimensional data manipulation

Abstract: The monolithic three-dimensional integration of memory and logic circuits could dramatically improve the performance and energy efficiency of computing systems. Some conventional and emerging memories are suitable for vertical integration, including highly scalable metal-oxide resistive switching devices (“memristors”). However, the integration of logic circuits has proven to be much more challenging than expected. In this study, we demonstrated memory and logic functionality in a monolithic three-dimensional circuit by adapting the recently proposed memristor-based stateful material implication logic. By modifying the original circuit to increase its robustness to device imperfections, we experimentally showed, for the first time, a reliable multi-cycle multi-gate material implication logic operation and half-adder circuit within a threedimensional stack of monolithically integrated memristors. Direct data manipulation in three dimensions enables extremely compact and high-throughput logicin- memory computing and, remarkably, presents a viable solution for the Feynman Grand Challenge of implementing an 8-bit adder at the nanoscale.

DNA based arithmetic function: a half adder based on DNA strand displacement.

Abstract: Biomolecular programming utilizes the reactions and information stored in biological molecules, such as proteins and nucleic acids, for computational purposes. DNA has proven itself an excellent candidate for building logic operating systems due to its highly predictable molecular behavior. In this work we designed and realized an XOR logic gate and an AND logic gate based on DNA strand displacement reactions. These logic gates utilize ssDNA as input and output signals. The XOR gate and the AND gate were used as building blocks for constructing a half adder logic circuit, which is a primary step in constructing a full adder, a basic arithmetic unit in computing. This work provides the field of DNA molecular programming with a potential universal arithmetic tool.

Improved design of all-optical photonic crystal logic gates using T-shaped waveguide

Abstract: In this paper, we propose new structures of all-optical logic gates based on two-dimensional photonic crystal of square type lattice with Si rods in air background. The proposed structures are based on T-shaped waveguide with optimized edge rod radius. An extra reference input port is included in the structure along with the actual input ports required for a logic gate. The simulation results show that the proposed T-shape waveguide can work as a NOT gate and a dual T-shape waveguide can work as NOR, XNOR and NAND gate with proper change in the phase values of logic ‘1’ input. The proposed structures have fast response time with value not more than 0.35 ps. The size of these structures is also small. It is expected that these new T-shaped structure based all-optical logic gates are suitable for large scale optical integration and can potentially be used in on-chip photonic integrated circuits.

A secure camouflaged threshold voltage defined logic family

Abstract: A myriad of security vulnerabilites can be exposed via the reverse engineering of the integrated circuits contained in electronics systems. The goal of IC reverse engineering is to uncover the functionality and internal structure of the chip via techniques such as depackaging/delayering, high-resolution imaging, probing, and side-channel examination. With this knowledge, an attacker can more efficiently mount various attacks, clone/-counterfeit the design possibly with hardware Trojans inserted, and discover trade secrets. We propose a gate camouflaging technique that relies on the usage of different threshold voltage transistors, but with identical layouts, to determine the logic gate function. In our threshold voltage defined (TVD) camouflaging technique, every TVD logic gate has the same physical structure and is one time mask programmed with different threshold implants for different boolean functionality. We design and implement TVD logic gates in an industrial 65nm bulk CMOS process. Using post-layout extracted simulation, we evaluate the logic style for VLSI overheads (area, power, delay) versus conventional logic, for process variablity robustness, and for various security metrics. Further, we evaluate the macro block overheads for ISCAS benchmark designs under various levels of TVD gate replacement upto and including 100% replacement. TVD logic gates are found to be CMOS process compatible, low overhead, and to increase security against various forms of attacks.

Sub-kBT micro-electromechanical irreversible logic gate.

Abstract: In modern computers, computation is performed by assembling together sets of logic gates. Popular gates like AND, OR and XOR, processing two logic inputs and yielding one logic output, are often addressed as irreversible logic gates, where the sole knowledge of the output logic value is not sufficient to infer the logic value of the two inputs. Such gates are usually believed to be bounded to dissipate a finite minimum amount of energy determined by the input-output information difference. Here we show that this is not necessarily the case, by presenting an experiment where a OR logic gate, realized with a micro-electromechanical cantilever, is operated with energy well below the expected limit, provided the operation is slow enough and frictional phenomena are properly addressed.

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Abstract: In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

Hybrid STT-CMOS designs for reverse-engineering prevention

Abstract: This paper presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design reverse engineering. Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). STT-based LUT with significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT-based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. Our study conducted on a large number of standard circuit benchmarks concludes significant resiliency of hybrid STT-CMOS circuits against various types of attacks. Furthermore, the selection algorithms on average have a small impact of less than 3%, 8%, and 3% on design parametric constraints including performance, power and area, respectively.

An energy-efficient random number generator for stochastic circuits

Abstract: Stochastic circuits provide very high efficiency in terms of gate area and power consumption compared with conventional binary logic. However, they require random bit streams generated by stochastic number generators (SNGs), which account for a significant portion of area and energy offsetting their merits. In this paper, we propose a new SNG that significantly reduces area and energy while improving accuracy in progressive precision. Experimental results show that the proposed SNG reduces energy by more than 72% compared to the state-of-the-art designs.

High performance ternary adder using CNTFET

Abstract: This paper presents two new designs to implement a ternary half adder using Carbon Nanotubes Field Effect Transistors (CNFETs). Ternary logic is a promising alternative to conventional binary logic, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to reduced circuit overhead such as interconnect and chip area. In this paper the authors are presenting two different novel ternary half adder circuits using ternary decoders and binary logic gates. The circuits are simulated using HSPICE to obtain power, delay and power delay product. The circuit performances are compared with the recently reported designs. The proposed ternary adders show delay and power advantage up to 40 and 39% with less transistor count. So, use of these half adders in complex arithmetic circuits will be advantageous.

Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication

Abstract: Memristors are considered among the most promising future building blocks of next-generation digital systems. This paper focuses on specific ways to implement logic and arithmetic unit using memristors. In particular, we present a set of complementary resistive switching (CRS)-based stateful logic operations that use material implication to provide the basic logic functionalities needed to realize logic circuits. The proposed solution benefits from the exponential reduction in sneak path current in crossbar implemented logic. This paper also presents a closed-form expression for sneak current and analyzes the impact of device variation on the behavior of the proposed logic blocks. Our technique, as other similar techniques proposed in the literature, requires several sequential steps to perform the computation. However, in this paper, we show that only three steps are required for implementing N input nand gate, whereas previously proposed memristor-based stateful logic needs N + 1 steps. We validated the effectiveness of our solution through cadence spectre circuit simulator on a number of logic circuits. Finally, we extended this approach for arithmetic circuits with an 8-bit adder and a 4-bit multiplier.

Compact photonic crystal integrated circuit for all-optical logic operation

Abstract: Photonic integrated circuits (PICs) will be pushed to electronic integrated circuits in the forthcoming decade because of its package density, interconnections, improved functionality and cost effectiveness. In this study, the authors propose a new configuration of photonic crystal (PhC) integrated circuits to realise the operation of all-optical logic AND function that operates at a speed of hundreds of gigabits per second. The integrated circuit comprises of lasers, waveguide couplers, logic gate, amplifier and threshold limiter in a two-dimensional (2D) silicon PhC platform. The behaviour of the proposed structure is qualitatively analysed by the use of 2D finite-difference time-domain method. The results show that the integrated circuit performs the required logic operation. The average area required for the entire device including regenerated circuit is 25 × 10 μm 2 . The overall response time is <;2 ps. This device is one of the promising platforms for future optical computers and optical signal processor.

Gate-level netlist reverse engineering for hardware security: Control logic register identification

Abstract: The heavy reliance on third-party resources, including third-party IP cores and fabrication foundries, has triggered the security concerns that design backdoors and/or hardware Trojans may be inserted into fabricated chips. While existing reverse engineering tools can help recover netlist from fabricated chips, there is a lack of efficient tools to further analyze the netlist for malicious logic detection and full functionality recovery. While it is relatively easy to identify the functional modules from the netlist using pattern matching methods, the main obstacle is to isolate control logic registers and reverseengineering the control logic. Upon this request, we proposed a topology-based computational method for register categorization. Through this proposed algorithm, we can differentiate data registers from control logic registers such that the control logic can be separated from the datapath. Experimental results showed that the suggested method was capable of identifying control logic registers in circuits with various complexities ranging from the RS232 core to the 8051 microprocessor.

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Abstract: In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

A hybrid memristor-CMOS XOR gate for nonvolatile logic computation

Abstract: Memristor-based logic gates that can execute memory and logic operations are promising elements for building non-von Neumann computation architecture. In this paper, we proposed a fundamental hybrid memristor-CMOS nonvolatile XOR Boolean logic block with one memristor and four voltage-controlled switches, such as MOSFET or transmission gate. The Ag/Ag5In5Sb60Te30/Ta structure memristors with bipolar resistive switching behaviors were utilized to experimentally demonstrate the XOR function of the block. Further, with the XOR logic block as a basis, a full adder as an extensive circuit example was designed and verified by HSPICE simulation. Our work shows logic-in-memory capabilities with memristors, and provides an alternative way to implement nonvolatile logic operations and construct parallel computation systems.

Memristor based unbalanced ternary logic gates

Abstract: This paper introduces a novel design of basic ternary logic gates using memristor, which is a set of AND, OR, inverters, NOR, and NAND gates. The ternary logic is a promising alternative to the conventional binary logic design technique. The resistive-load MOSFET-based ternary logic gates have already been proposed. The proposed memristor-based circuit replaces the large resistors by employing active load memristor in the ternary logic gates. The proposed ternary logic circuits are shown to have great significant advantages relative to other known binary circuits and ternary circuits like low power dissipation, chip area, component count, dense fabrication and cost. The paper concludes with an implementation of the ternary logic gates using SPICE simulations.

Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits

Abstract: We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors in series. This leads to topological differences and increased flexibility in circuit design. We found that especially complex functions, like Majority and Parity gates of many inputs, which are generally avoided in standard CMOS technology, benefit from the new device type. This can be exploited to directly map reconfigurable building blocks, e.g. dynamically switching NAND to NOR. Exemplary 6-functional logic circuits will be shown, which exhibit up to 80% reduction in transistor count, while maintaining the same functionality as compared to the CMOS reference design. Logical effort analysis indicates that 20% less circuit delay and 33% less normalized dynamic power consumption can be achieved.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

Abstract: An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated.

Graph-Based Transistor Network Generation Method for Supergate Design

Abstract: Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series–parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

All Optical Scalable Logic Gates Using Si 3 N 4 Microring Resonators

Abstract: In this paper, microring resonator-based logic gates are discussed that operate on same input and output wavelength. Same input and output wavelength allows the cascaded operation of the developed logic gates and thus can be utilized for developing photonic integrated circuits. Logic operations such as and , or , nor , xor , and xnor are successfully demonstrated. Optical Kerr effect is utilized for operation and structures are numerically simulated using coupled mode equations. Output power levels of around 0.18 and 0.05 W are achieved for high- and low-power logic, respectively. The proposed structures perform well for data rate under 1 Gbps and are analyzed to determine the acceptable input range for high- and low-power logic, respectively. The cascaded operation of proposed logic gates is also demonstrated.

Design and performance analysis of multiple all optical logic gates in a single photonic circuit

Abstract: The model discussed in this paper is of multiple optical logic gates in a single photonic circuit. NAND, AND, NOR, OR, XOR, XNOR, NOT gates are incorporated in the design. The outputs of these gates are on different wavelengths of conventional band, from 1550 to 1560 nm. The gates are achieved by using 2 × 2 coupler with different coupling coefficient, multiplexer and the nonlinearities of SOA, which are otherwise regarded as demerit if SOA is used as an amplifier. The performance of the suggested model is analyzed through extinction ratio and quality factor, recorded for different values of length and confinement factor of SOA. Results of each individual gate are analyzed. The growth of all optical multiple logic functions onto a single chip is leading towards complex photonic computing and gradually eliminating the need for opto-electric conversions.

Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration

Abstract: The high power and the long global interconnect delay are two of the major bottlenecks that limit the further scaling down of the process nodes in the VLSI systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and the interconnect delay. Current-induced magnetic domain-wall (DW) racetrack memory (RM) has the advantages of nonvolatility, fast switching speed, and high density. It may offer opportunities to open a new paradigm of circuits and architectures to significantly alleviate the power and delay issues. This paper presents the magnetic DW RM-based new nonvolatile logic designs for the low-power computing and fast run-time-reconfiguration. Both data transfer and reconfiguration are achieved by shifting the magnetic strips. Verify-before-shift approach is used to greatly reduce the shifting energy. Compared with the conventional nonvolatile logic gate, the proposed nonvolatile logic scheme doubles the operating speed with 87% lower operating energy. Moreover, the proposed nonvolatile logic gates can be reconfigured after fabrication, which makes the designs more flexible and robust. The reference reconfiguration and the polarity reconfiguration are presented in this paper, which can be finished in 1 ns with 130 fJ/strip energy and 6 ns with 390 fJ/strip energy, respectively.