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Showing papers on "Pass transistor logic published in 2018"


Journal ArticleDOI
TL;DR: An ultra-low voltage level shifter (LS) with fast and energy-efficient voltage conversion from the deep subthreshold region to the superth threshold region is presented with better performance and increased energy efficiency by addressing the reduced swing and the slow fall transition issues in prior arts.
Abstract: This brief presents an ultra-low voltage level shifter (LS) with fast and energy-efficient voltage conversion from the deep subthreshold region to the superthreshold region. The proposed LS achieves better performance and increased energy efficiency by addressing the reduced swing and the slow fall transition issues in prior arts. A novel reduced-swing buffer design is proposed to attain lower standby power consumption while a pass transistor is used for improving the speed of the fall transition. The proposed LS consists of only 11 transistors occupying $7.45~ {\mu }\text{m}^{2}$ , which obtains the smallest area among the state-of-the-art ultra-low voltage LSs. Measurement results from a test chip fabricated in 65-nm CMOS technology demonstrate that the proposed LS shows the maximum leakage and speed improvements of $16.3{\times}$ and $2.7{\times}$ compared to the Wilson current mirror LS. The proposed LS also accomplishes the maximum switching energy reduction of $8.5{\times}$ and can convert deep subthreshold voltage as low as 100 mV to the superthreshold voltage of 1.2 V.

49 citations


Journal ArticleDOI
TL;DR: In this article, a full-swing, low-power and energy-aware full-adder using hybrid logic scheme is presented, where a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T xOR-xNOR gates combined with a feedback loop.

47 citations


Journal ArticleDOI
TL;DR: A mapping methodology of large Boolean logic circuits on memristor crossbar, as well as several optimization schemes are proposed to efficiently map the circuits on the crossbar.
Abstract: Alternatives to CMOS logic circuit implementations are under research for future scaled electronics. Memristor crossbar-based logic circuit is one of the promising candidates to at least partially replace CMOS technology, which is facing many challenges such as reduced scalability, reliability, and performance gain. Memristor crossbar offers many advantages including scalability, high integration density, nonvolatility, etc. The state-of-the-art for memristor crossbar logic circuit design can only implement simple and small circuits. This paper proposes a mapping methodology of large Boolean logic circuits on memristor crossbar. Appropriate place-and-route schemes, to efficiently map the circuits on the crossbar, as well as several optimization schemes are also proposed. To illustrate the potential of the methodology, a multibit adder and other nine more complex benchmarks are studied; the delay, area and power consumption induced by both crossbar and its CMOS control part are evaluated.

30 citations


Journal ArticleDOI
TL;DR: In this paper, the authors proposed the realization of all-optical NAND and NOR logic functions on a single photonic crystal structure by cascading basic logic gates, viz. AND, OR, and NOT.
Abstract: In this article, we propose the realization of all-optical NAND and NOR logic functions on a single photonic crystal structure by cascading basic logic gates, viz. AND, OR, and NOT. Initially, to achieve this, a photonic crystal logic gate structure is designed with cross-shaped waveguide as a common gate for AND and OR functions, and another photonic crystal structure is devised with T-shaped waveguide as NOT gate. An additional input, namely reference input, is applied to these basic gate structures whose phase determines the type of the logic function in the former gate structure, and inevitable for NOT function in the latter one. The reference input is out of phase with the actual inputs in AND and NOT functions, whereas it is inphase in OR function. Simulation results show that the contrast ratio for AND, OR, and NOT is 11.74, 9.99, and 54.52 dB, respectively, with a response time of less than 0.15 ps. Later, these logic gate structures are cascaded to realize NAND and NOR functions, resulting a contrast ratio of 10.57 and 8.60 dB, respectively, at a response time of 0.152 ps. The percentage of reduction in the contrast ratio of the cascaded structure compared with the basic AND/OR gate is very small with a value of less than 1.5%. Moreover, the proposed NAND/NOR logic gate obtained by cascading the basic logic gates is quite compact with area occupancy lowered by a factor of 4.5 compared to the cascaded structures available in the literature.

25 citations


Journal ArticleDOI
TL;DR: It was found that recovery of dissipated power using adiabatic logic was better than the other CAM structures and the simulation results of the PEBCAM-IECRL CAM proved to be better with a power saving of 77.8% than the conventional adiABatic CAM structures.
Abstract: This paper presents the design and the analysis of power efficient binary content addressable memory (PEBCAM) core cells using the energy recovery principle of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is built by using a basic CAM cell, but the peripheral circuits are realized by using different adiabatic logic structures. In this paper, we propose the design of 3 novel power efficient binary content addressable memory core cells (PEBCAM core cells) using adiabatic logic, namely improved efficient charge recovery logic (IECRL) CAM core cell, positive feedback adiabatic logic (PFAL) CAM core cell and pass transistor adiabatic logic (PAL) CAM core cell. Memory arrays of size 4 $$\times $$? 4 were designed and implemented using the proposed PEBCAM core cells in 45nm CMOS technology. It was found that recovery of dissipated power using adiabatic logic was better than the other CAM structures. The simulation results of the PEBCAM-IECRL CAM proved to be better with a power saving of 77.8% than the conventional adiabatic CAM structures. The circuits were designed using 45nm CMOS technology with a sinusoidal power clock of 1 V and other node voltages at 0.7 V using Cadence Virtuoso.

21 citations


Journal ArticleDOI
TL;DR: In this article, current mode logic gates using Magnetic tunnel junction (MTJ) elements without any intermediate electronic circuitry have been presented to reduce the performance overheads of the spintronic logic circuits while simplifying fabrication.
Abstract: Non-volatile logic is a viable solution to overcome the leakage power issue which has become a major obstacle to CMOS technology scaling Magnetic tunnel junction (MTJ)-based logic is a promising approach because of the non-volatility, less occupied area, almost zero static power consumption, programmability This paper presents current mode logic gates using MTJ elements without any intermediate electronic circuitry This efficient solution reduces the performance overheads of the spintronic logic circuits while simplifying fabrication Hspice based simulations have been carried out to verify the performance of different logic gates The simulation results reveal that the SBEG based gates provide less area, power consumption, and energy while also offering less design complexity as compared to mLogic (previously proposed magnetic logic) and CMOS gates

20 citations


Journal ArticleDOI
TL;DR: Simulation results for various test circuits indicate upto 35.1% and 63.8 % improvement in power-delay product (PDP) and PDAP respectively in 130 nm/1.2 V TSMC CMOS technology.

13 citations


Proceedings ArticleDOI
23 Jul 2018
TL;DR: Experimental demonstration of transistor threshold voltage-defined switch [2] based camouflaged logic gates that can hide six logic functionalities i.e. NAND, AND, NOR, OR, XOR and XNOR are presented.
Abstract: Due to the ever-increasing threat of Reverse Engineering (RE) of Intellectual Property (IP) for malicious gains, camouflaging of logic gates is becoming very important In this paper, we present experimental demonstration of transistor threshold voltage-defined switch [2] based camouflaged logic gates that can hide six logic functionalities ie NAND, AND, NOR, OR, XOR and XNOR The proposed gates can be used to design the IP, forcing an adversary to perform brute-force guess-and-verify of the underlying functionality---increasing the RE effort We propose two flavors of camouflaging, one employing only a pass transistor (NMOS-switch) and the other utilizing a full pass transistor (CMOS-switch) The camouflaged gates are used to design Ring-Oscillators (RO) in ST 65nm technology, one for each functionality, on which we have performed temperature, voltage, and process-variation analysis We observe that CMOS-switch based camouflaged gate offers a higher performance (~15-8X better) than NMOS-switch based gate at an added area cost of only 5% The proposed gates show functionality till 065V We are also able to reclaim lost performance by dynamically changing the switch gate voltage and show that robust operation can be achieved at lower voltage and under temperature fluctuation

11 citations


Journal ArticleDOI
TL;DR: Two realisations each using 2-pass transistors/2-transmission gates and 2-inverters for Hamming-code generation achieve a full rail-to-rail swing, high performance and high noise margin at low voltages.
Abstract: The XOR/XNOR gates are basic building blocks for various digital systems like adders, comparators, multipliers, parity-generator/checker and encryption processor. This paper proposes two realisations each using 2-pass transistors/2-transmission gates and 2-inverters. All the proposed circuits are simulated and compared with existing circuits using Cadence Spectre on both 180 and 90 nm CMOS technology with varying supply rail (from +0.8 V to +1.8 V). The simulation results confirm that the proposed circuits achieve a full rail-to-rail swing, high performance and high noise margin at low voltages. Analytical expressions in support of simulation-results wherever required are included. A typical application in Hamming-code generation is proposed.

10 citations


Journal ArticleDOI
TL;DR: Three novel designs for single-stage, 3-input XOR logic cells are proposed and the TG-based design reports best performance while the PT-based designs follow as closed second with better component economy and control input overload.
Abstract: In this paper, three novel designs for single-stage, 3-input XOR logic cells are proposed. The design uses either Transmission Gate (TG) or Pass Transistor (PT) on similar topologies. The proposed ...

9 citations


Journal ArticleDOI
TL;DR: The mPLD-XOR with feedback can reduce the size and number of computational steps (clock cycles) in realizing logic functions, which makes it well suited for use in communication and parallel computing systems where fast arithmetic operations are demanding.
Abstract: This paper describes a CMOS-memristive programmable logic device connected to CMOS XOR gates (mPLD-XOR) for realizing multioutput functions well suited for two-level {NAND, AND, NOR, OR}-XOR-based design. This structure is a generalized form of AND–XOR logic where any combination of NAND, AND, NOR, and OR, and literals can replace the and level. For mPLD-XOR, the computational delay, which is measured as the number of clock cycles, equals the maximum number of inputs to any output XOR gate of a function assuming that the number of XOR gates is large enough to calculate the outputs of the function simultaneously. The input levels of functions are implemented with novel programmable diode gates, which rely on the diode-like behavior of self-rectifying memristors, and the output levels of functions are realized with CMOS modulo-two counters. As an example, the circuit implementation of a 3-bit adder and a 3-bit multiplier are presented. The size and performance of the implemented circuits are estimated and compared with those of the equivalent circuits realized with stateful logic gates. Adding a feedback circuit to the mPLD-XOR allows the implementation of a multilevel XOR logic network with any combination of sums, products, XORs, and literals at the input of any XOR gate. The mPLD-XOR with feedback can reduce the size and number of computational steps (clock cycles) in realizing logic functions, which makes it well suited for use in communication and parallel computing systems where fast arithmetic operations are demanding.

Journal ArticleDOI
TL;DR: In this paper, the authors proposed circuit design methodologies to enhance the electromagnetic immunity of an output-capacitor-free low-dropout (LDO) regulator in the small-signal domain, powersupply rejection (PSR) is used.
Abstract: This paper presents circuit design methodologies to enhance the electromagnetic immunity of an output-capacitor-free low-dropout (LDO) regulator. To evaluate the noise performance of an LDO regulator in the small-signal domain, power-supply rejection (PSR) is used. We optimize a bandgap reference circuit for optimum dc PSR, and propose a capacitor cancelation technique circuit for bandwidth compensation, and a low-noise biasing circuit for immunity enhancement in the bias circuit. For large-signal, transient performance enhancement, we suggest using a unity-gain amplifier to minimize the voltage difference of the differential inputs of the error amplifier, and an auxiliary N-channel metal oxide semiconductor (NMOS) pass transistor was used to maintain a stable gate voltage in the pass transistor. The effectiveness of the design methodologies proposed in this paper is verified using circuit simulations using an LDO regulator designed by 0.18- $\mu$ m CMOS process. When sine and pulse signals are applied to the input, the worst dc offset variations were enhanced from 36% to 16% and from 31.7% to 9.7%, respectively, as compared with those of the conventional LDO. We evaluated the noise performance versus the conducted electromagnetic interference generated by the dc–dc converter; the noise reduction level was significantly improved.

Journal ArticleDOI
Jeongje Moon1, Jeongje Moon2, Yoonjoong Kim1, Doohyeok Lim1, Sangsig Kim1 
TL;DR: In this article, a bendable metal-oxide−semiconductor (CMOS) NOR logic gate consisting of silicon nanowire (NW) arrays on bendable substrates is proposed.
Abstract: In this study, we propose complementary metal-oxide−semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately −3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.

Journal ArticleDOI
TL;DR: A novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application and the results demonstrate a noteworthy change in leakage power utilization and speed.
Abstract: Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.

Proceedings ArticleDOI
06 Apr 2018
TL;DR: A hybrid J-bit full adder design which employs both static CMOS logic and Swing Restoring Pass Transistor Logic (SRPL) is presented, which not only reduces the complexity but also offers multiple fold reduction in PDP.
Abstract: Modern VLSI techniques focus greatly on High Speed Propagation and Low Power Consumption. In this research paper, we present a hybrid J-bit full adder design which employs both static CMOS logic and Swing Restoring Pass Transistor Logic (SRPL). We have compared our work against other state of art designs, for power consumption, speed and area constraints. We designed all the full-adders in Mentor Graphics Tanner Il.LSum CMOS technology. At 1.8V power supply, the average power consumed by our design is 3.69f.lW, at 100MHz and the propagation delay 0.21 ns. Beyond all doubts, our design not only reduces the complexity but also offers multiple fold reduction in PDP.

Journal ArticleDOI
TL;DR: This work proposes a clock-less, self-timed ATPG for NCL with no area overhead, and investigates the effectiveness of I_DDQ (quiescent current) test for detecting stuck-at faults on GIF of NCL gates.
Abstract: Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of I_DDQ (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I_DDQ testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I_DDQ test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clock-less, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I_DDQ test for NCL.

Patent
21 Jun 2018
TL;DR: In this article, a bit cell for a static random access memory (SRAM) comprising of a first and a second vertical stack of transistors arranged on a substrate is presented. But the bit cell is not designed to be used in a real-world application.
Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected. A source/drain of the pull-up transistor and of the pull-down transistor of the second stack, a source/drain of the pass transistor of the second stack and the common gate electrode of the pull-up and pull-down transistors of the first stack are electrically interconnected.

Journal ArticleDOI
TL;DR: An attempt has been made to reduce the overhead power, delay and area of FEC codes: hamming code and dual rail code, and error detecting codes: checksum and two-dimensional parity with duplication and it is observed that error controlling schemes are providing the best performance with pass transistor logic overerror controlling schemes with CMOS logic.
Abstract: System-on-ship (SoC) design in the nanoelectronics era brings us not only many opportunities but also several challenges like synchronization, process uncertainty, global interconnecting delay, high scalability, and reliability. Network on Chip (NoC) could be a communication subsystem and it is rising as a revolutionary design methodology to solve the problems associated with SoC designing. Reliability is one of the major designing challenges in NoC design under technology limitations at low voltage operations and under the influence of very deep sub-micron noise sources, including crosstalk noise. To achieve the reliability of NoC, error controlling codes (ECC) are required. ECCs are broadly categorized as forward error correcting (FEC) codes and error detection codes. ECC improves the reliability of NoC with a penalty of overhead power, delay, and area. In this paper, an attempt has been made to reduce the overhead power, delay and area of FEC codes: hamming code and dual rail code, and error detecting codes: checksum and two-dimensional parity with duplication. These ECC are designed in 65 nm technology using CMOS and pass transistor logic and their power–reliability trade-off is analyzed and compared in terms of delay and overhead area. From the results, it is observed that error controlling schemes are providing the best performance with pass transistor logic over error controlling schemes with CMOS logic.

Journal ArticleDOI
TL;DR: This paper explores a new circuit structure called RF-only logic that permits logic circuits to operate directly from an un-rectified RF source and demonstrates performance improvement and overall area overhead of 16% by implementing the power-supply transistor sharing algorithm.
Abstract: Reducing circuit design cost and eliminating over-design margin are the two challenges for advancing the Internet of Things (IoT). An RF-dc rectifier and storage capacitors consume 25% or more of the chip area for cost-sensitive power-harvesting-enabled IoT applications. In this paper, we explore a new circuit structure called RF-only logic that permits logic circuits to operate directly from an un-rectified RF source. By eliminating the need for RF-dc rectifier and storage capacitors, RF-only logic helps to reduce cost and design complexity for power-harvesting-enabled applications. The structure and operations of RF-only logic are presented. Its performance, power consumption, and robustness are analyzed through simulation and validated with measurement results. A standard cell library was developed for RF-only logic, and an algorithm was implemented to further improve area efficiency. A ring oscillator and two $4\times 4$ multipliers were fabricated in 0.13- $\mu \text{m}$ CMOS as test structures. The ring oscillator was functionally measured with an RF supply voltage down to 100-mVrms at 1 GHz. The multipliers demonstrate performance improvement and overall area overhead of 16% by implementing the power-supply transistor sharing algorithm.

Journal ArticleDOI
TL;DR: A new combination of multiplier method with low power and low delay is produced and satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra.
Abstract: Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps.

Patent
20 Sep 2018
TL;DR: In this article, a pass transistor is configured to linearly transfer the input signal to the first node in response to a voltage level of input signal being below a first voltage level and configured to transfer a voltage-limited version of the input signals to the second node when the voltage level is above the first level.
Abstract: An integrated circuit includes an input terminal configured to receive an input signal, a reference voltage node configured to provide a control voltage, and a pass transistor comprising a first terminal coupled to a first node, a control terminal coupled to the reference voltage node, and a second terminal coupled to the input terminal. The control voltage has a control voltage level sufficient to allow a signal to pass from the second terminal to the first terminal. The pass transistor is configured to linearly transfer the input signal to the first node in response to a voltage level of the input signal being below a first voltage level and configured to transfer a voltage-limited version of the input signal to the first node in response to the voltage level being above the first voltage level. At most, a negligible DC current flows through the input terminal into the second terminal.

Patent
23 Aug 2018
TL;DR: In this paper, a voltage regulator with a pass transistor for providing the load current at the output node from an input node is presented, where the driver stage has a current amplifier amplifying a drive current through the drive transistor to provide an amplified current through a diode transistor.
Abstract: A voltage regulator to provide a load current at an output node is presented. The voltage regulator has a pass transistor for providing the load current at the output node from an input node. The voltage regulator contains a driver stage to set a gate voltage at a gate of the pass transistor based on a drive voltage at a gate of a drive transistor. The voltage regulator has voltage regulation means to set the drive voltage in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage. The driver stage has the drive transistor and a diode transistor, wherein the diode transistor forms a current mirror with the pass transistor. The driver stage has a current amplifier amplifies a drive current through the drive transistor to provide an amplified current through the diode transistor.

Proceedings ArticleDOI
01 Oct 2018
TL;DR: A novel 1 bit energy efficient hybrid adder has been introduced which can optimize performance parameters like power and delay of two CMOS hybrid full adder circuits described in this paper.
Abstract: In this paper a novel 1 bit energy efficient hybrid adder has been introduced which can optimize performance parameters like power and delay of two CMOS hybrid full adder circuits described in this paper. The first described design is implemented with normal Complementary metal oxide semiconductor (CMOS) and second design is a hybrid model of CMOS and transmission gate logic (CMOS-TGL). The proposed model is hybridized with Complementary metal oxide semiconductor, pass transistor and modified gate diffusion input logics (CMOS-PT-MGDI) together to ensure low power and high speed. The performance parameters such as power, delay and area of 1 bit full adders was analyzed and tabulated. All the circuits were implemented using cadence virtuoso tool in 90nm technology for 1.2V supply.

Book ChapterDOI
01 Jan 2018
TL;DR: In this research work, a hybrid low-power 1-bit full adder was designed using CMOS logic, pass transistor, and transmission gate logic with 14 transistor and found that the proposed adder has the low- power consumption and power delay product than the existing adders.
Abstract: The usage of digital devices is increasing rapidly and they became essential part of everyone’s life. Digital devices can be designed according to their application and most of them are realized using arithmetic processor which consists of several operations like addition, subtraction, multiplication, etc., all of them can be implemented using full adder as the basic building block. As full adder plays a major role in digital devices we need to design a low-power full adder such that the devices can operate at lower power consumption and has longer battery life. In this research work, a hybrid low-power 1-bit full adder was designed using CMOS logic, pass transistor, and transmission gate logic with 14 transistor. The design was simulated using HSPICE tools in 90 nm technology with supply voltage of 1.2 V. Performance parameters, such as power, delay, and power delay product were compared with the existing designs, such as C-CMOS Full Adder, Mirror adder, hybrid pass-logic with static CMOS output drive full adder and found that the proposed adder has the low-power consumption and power delay product than the aforementioned adders.

Patent
20 Sep 2018
TL;DR: In this article, a low-dropout regulator with multiple supply voltages is described, where the gate of the pull-down transistor and gate of a feedback switch are configured to receive a bypass signal.
Abstract: Regulation/Bypass automation for a low drop-out regulator (LDO) with multiple supply voltages is disclosed. In some implementations, a LDO includes a resistor, a pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to a first terminal of the resistor; a feedback switch having a drain, a gate, and a source, the drain coupled to a second terminal of the resistor, the source coupled to a negative input of the OTA; and an pull-down transistor having a drain, a gate, and a source, the source coupled to ground, and the drain coupled to the negative input of the OTA, wherein the gate of the pull-down transistor and the gate of the feedback switch are configured to receive a bypass signal.

Patent
Zou Lei1, Rocca Gino
27 Mar 2018
TL;DR: In this article, a low-dropout voltage regulator (LDO) is described, which includes a voltage input connectable to a power supply, an error amplifier coupled to the voltage input and configured to generate an output control signal dependent on the reference signal and the feedback signal.
Abstract: A low-dropout voltage regulator (LDO) apparatus is disclosed. In an embodiment, the LDO apparatus includes a voltage input connectable to a power supply, an error amplifier coupled to the voltage input and configured to receive a reference signal and a feedback signal and to generate an output control signal dependent on the reference signal and the feedback signal, and a pass transistor coupled to the error amplifier and configured to receive the output control signal of the error amplifier and to provide an output current dependent on the output control signal. The LDO apparatus further includes a detection circuit coupled to the voltage input and configured to provide an output signal on its output and a bias generator coupled to the output of the detection circuit and configured to provide a bias current on a bias input of the current adjusting circuit of the error amplifier.

Book ChapterDOI
01 Jan 2018
TL;DR: The proposed design of the 2-bit Vedic multiplier has been designed using pass transistor logic and is the fastest, reliable, efficient, and low-power multipliers.
Abstract: The requirement of a high-speed multiplier is expanding. It is one of the most important hardware blocks in a processing system. A multiplier acts as a high delay block, and it also dissipates a lot of power. An ordinary processor requires more time and resources in multiplication operation. The proposed design of the 2-bit Vedic multiplier has been designed using pass transistor logic. The Vedic multiplier is the fastest, reliable, efficient, and low-power multipliers. By reducing the number of partial products, the delay also decreased and the system becomes faster. The design and the properties of this multiplier have been studied and performed using the Pyxis Schematic software (90 nm), and the power dissipation and delay have been compared with 2-bit multiplier using CMOS logic. The analysis is made for voltage range from 0.8 to 1.5 V.

Proceedings ArticleDOI
01 Aug 2018
TL;DR: This paper proposes CMOS/Pass Transistor Logic based approximate multiplier (MCPAM), a transistor level 2 by 2 novel approximate multiplier with minimum error distance and compact architecture that is to use static CMOS style and PTL logic together for low area/power design implementation.
Abstract: Approximate computing permits compromise on the accuracy of output of computational circuits to reduce the area of these circuits and lessen their power consumption. However, the acceptability of inexact output is an application specific phenomenon. In this paper, we particularly address the case of multiplier design such that features of accuracy and low area/power are equally sought, by proposing CMOS/Pass Transistor Logic (PTL) based approximate multiplier (MCPAM). MCPAM is a transistor level 2 by 2 novel approximate multiplier with minimum error distance and compact architecture. In case of applications with exact output requirements, MCPAM can be configured for accuracy through a proposed low-cost error detection and correction mechanism. The novelty of the method lies in the design of approximate multiplier that is to use static CMOS style and PTL logic together for low area/power design implementation. Experimental results and comparative analysis using 45nm demonstrate 60% to 83.6% and 71.3% improvement in power and area, respectively, as compared with previously proposed approximate multiplier. When MCPAM is used in conjunction with its error detection and correction unit, up to 37.4% and 17.3% reduction in area and power consumption, respectively, is observed as compared with previously proposed approximate multiplier employing error correction.

Proceedings ArticleDOI
01 Mar 2018
TL;DR: Experimental results reveal that the proposed circuits present a significant improvement in terms of power, delay and transistor count and it outperforms the conventional CMOS based design.
Abstract: A unique idea based on mixed-logic design for line decoder is designed by connecting transmission gate logic, pass transistor dual-value logic and static CMOS. Conventional techniques use static CMOS circuit to implement the design. However the power dissipation is observed to be high and the primary reason behind rise in power is due to increase in number of transistors. Here the proposed design uses mixed logic technique and GDI logic to build decoder which significantly decreases the transistor's count that results in low power consumption. Compared with mixed logic the GDI gives better result in power consumption and also delay reduction. Both normal and an inverting decoder designs are implemented. The proposed decoder can operate at low supply voltage and it finds its space in low power applications. Experimental results reveal that the proposed circuits present a significant improvement in terms of power, delay and transistor count and it outperforms the conventional CMOS based design.

Journal ArticleDOI
TL;DR: The proposed waveform-accurate SAT-based automatic test pattern generation (ATPG) framework can be used to generate tests for faults only detectable by hazard-based activation—and hence even increase the fault coverage beyond state-of-the-art cell-aware tests.
Abstract: Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today’s very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation—and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC’99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.