Showing papers on "Pass transistor logic published in 2019"

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Abstract: Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

Abstract: This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and red...

Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs

Abstract: Multimedia applications consume an immense amount of energy. These applications have division as one of the fundamental operations. Division is also one of the costliest operations in terms of energy consumption. Thus, various works have been done to address the issue of energy consumption in multimedia applications by using approximate dividers based on pass transistor logic (PTL). Since these applications have resilience towards erroneous computations huge energy benefits are obtained as a result of approximate computations with similar output quality. In this paper, we have shown that PTL based designs are not suitable for lower technology nodes. We performed an in-depth analysis using UMC 65nm and UMC 28nm to highlight the adverse effects of technology scaling on energy consumption and delay in PTL based design as compared to CMOS based designs. We also propose four different inexact CMOS subtractor (ICS) designs, as they are the basic repeated module in inexact restoring array dividers (IRADs). Our proposed ICS designs consume ~ 2× lesser dynamic energy, ~ 3× lesser static power and have ~ 2.5× lesser delay as compared to the existing PTL based designs in UMC 65nm. These benefits increase for UMC 28nm, which shows PTL based designs further worsens at lower technology nodes. IRADs also give about 50% reduction in energy consumption with only 3% degradation in Structural Similarity (SSIM) Index, an image quality metric in multimedia applications like change detection, background removal, and JPEG compression, as compared to exact restoring array divider (ERAD).

High‐speed, low power, and dead zone improved phase frequency detector

Abstract: Design of a novel phase frequency detector (PFD) has been presented here. The innovative advantage of the proposed structure is its improved dead zone performance due to the architectural simplicity which is a combination of static and pass transistor logic (PTL)-based latch configuration. Due to low latency from inputs to the outputs, the operating frequency of the proposed circuit is high while its power consumption is very low. Analytics along with simulations have confirmed the correct behaviour of the designed circuit. For better evaluation of designed architecture advantages, two of the last reported works have been redesigned and simulated along with the proposed PFD. The post-layout simulation results using HSPICE with TSMC 0.18 µm CMOS technology and 1.8 V power supply demonstrate the operating frequency of 1 GHz for the designed circuitry while the power dissipation is 277 µW and the measured dead zone is π / 11 as an enormous enhancement over previous works.

Design of a low power high speed 4-2 compressor using CNTFET 32nm technology for parallel multipliers

Abstract: In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller active area in the final realized circuit. Comparison with previous works depicts that the proposed structure has the lowest number of transistor among them. The proposed design has been designed and simulated in Carbon Nanotube Field-Effect Transistor (CNTFET) technology having 32nm channel dimension. The comparison with the best reported recent designs demonstrates the superiority of the proposed work; these reported designs in literature were simulated here in the same settings and process to perform a fair comparison. In addition, the Complementary Metal-Oxide-Semiconductor (CMOS) 32nm standard process has also been employed to realize the proposed circuit and to do the comparison between CMOS and CNTFET technologies which illustrates the advantage of CNTFET over standard CMOS processes. The transistor level delay for the critical path of the proposed design is equal to 4 transistors which is equal to the best reported work in the literature; however in the proposed work here the total number of transistors is reduced to 58 which according to the authors knowledge is the lowest numb reported for a 4-2 compressor block in the papers.

Fast-transient capacitor-less low-dropout regulator with input current-differencing and dynamic current-boosting

Abstract: Transient response improvement of a capacitor-less low-dropout regulator with input current-differencing is presented in this paper. The Miller compensation technique with series resistance is used to establish the stability and reduce the on-chip capacitor. As a result, the on-chip compensation capacitor of the proposed LDO is reduced to 4 pF which makes it suitable for portable SoC applications. The dynamic current-boosting technique is simultaneously applied to both the input current and the gate of the pass transistor to improve the line and load transient responses of the proposed LDO. The output voltage is regulated at 1 V with a dropout voltage of about 100 mV. The proposed circuit is simulated in TSMC 0.18 μm CMOS technology and its quiescent current is 42 μA. The simulation results of both the line and load transient responses show considerable improvement in the over/undershoot and the settling time of the proposed LDO as well as better transient performance compared to the similar previous works. The output voltage over/undershoot amplitudes of the proposed LDO are obtained 46/100 mV with the settling time of less than 2 μs for the load current changes from 0.1 to 100 mA with 1 µs rise/fall times.

Analysis of RF Noise in LDO and Establishment of Noise Immunity

Abstract: This paper presents the mechanism of RF noise propagation in a low-dropout regulator (LDO). Two dips in the output voltage in the range from 100 MHz to 1 GHz were confirmed by a direct power injection (DPI) method and a transverse electromagnetic (TEM) cell method. These characteristics were reproduced in simulation, and we observed that the inductance of the device wiring, parasitic elements of the pass transistor and the non-linearity of the OPAMP greatly contribute to the output drops. We established a method that is not affected by nonlinearity and succeeded in eliminating the drops in the output voltage.

A Wideband High PSRR Capacitor-Less LDO with Adaptive DC Level Shift and Bulk-Driven Feed-Forward Techniques in 28nm CMOS

Abstract: An analog solution of the capacitor-less low dropout regulator (CL-LDO) using the adaptive DC level shift (ADLS) and bulk-driven feed-forward (BDFF) techniques is proposed. The ADLS circuit is adopted to increase the headroom of the pass transistor's gate voltage, which achieves a larger current loading capability without increasing the size of the pass transistor. The BDFF technique decreases the threshold voltage of the pass transistor to improve its current driving capability and expand the bandwidth of the power supply rejection ratio (PSRR) by adding a feed-forward path at the pass transistor's bulk. The proposed LDO has been implemented in TSMC 28nm CMOS. The simulation results show that the proposed CL-LDO consumes 308 μA current from a 1.2–2.5V power supply, with a 0.7 to 0.9V output range. With 2pF internal capacitance, it can support 0–50mA load current within 80pF load capacitance range. The PSRR is under −20dB across 5MHz frequency range.

Design of Power Efficient Vedic Multiplier using Adiabatic Logic

Abstract: Various “arithmetic operations”, “signal and image processing systems” and “communication devices” incorporate multipliers as the basic element. Vedic mathematics is an ancient mathematical system which focuses on solving tedious problems using 16 Vedic Sutras in a simpler and faster manner. The evolution of technology demands for “low power design” in the domain of integrated circuit. This led to the invention of varied adiabatic logic for low power operations. The uniqueness of Vedic mathematics and adiabatic logic is combined to design high speed and power-efficient multipliers. In this paper, a new adiabatic logic “Complementary Pass Transistor Adiabatic Logic” (CPAL) is used to design 8-bit Vedic multiplier. To authenticate the superiority of the proposed design, comparative performance analysis is carried out with respect to CMOS and other adiabatic logics like 2N-2N2P and “Efficient Charge Recovery Logic” (ECRL) based on 150nm technology. The simulation has been accomplished by the use of TANNER SPICE 16 tool. Simulation result validates the reduction of Power Delay Product (PDP) of the proposed CPAL Vedic multiplier design in comparison to the aforementioned techniques. The proposed technology offers a power-efficient solution for modern designs.

Design and software characterization of finFET based full adders

Abstract: Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

High speed Radix-4 Booth scheme in CNTFET technology for high performance parallel multipliers

Abstract: A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology has been presented in this paper. The main advantage of the proposed scheme is its improved speed performance compared with previous designs. With the help of modifications applied to the encoder section using Pass Transistor Logic (PTL), the corresponding capacitances of middle stages have been reduced considerably. As a result, total transistor count along with power consumption has been decreased illustrating the other advantages of the designed structure. For evaluation of correct functionality, simulations using CNTFET 32nm standard process have been performed for the designed scheme which depict the latency of 195ps for critical path. Meanwhile, comparison with previous works using the Power Delay Product (PDP) criteria demonstrates the superiority of the proposed structure suggesting that our circuitry can be widely utilized for high speed parallel multiplier design.

Low-dropout regulator with load-adaptive frequency compensation

Abstract: A circuit comprises: a pass transistor; a first transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a second transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a first current mirror coupled to the drain of the first transistor; a second current mirror coupled to the drain of the second transistor, and coupled to the first current mirror; a feedback voltage circuit coupled to the drain of the pass transistor; an error amplifier comprising a first input port coupled to the feedback voltage circuit, and an output port coupled to the gate of the pass transistor; and a capacitor coupled to the second current mirror and to the first input port of the error amplifier.

The Research into Fault-Tolerant Design Usign Pass Transistor Logic

Abstract: this research is focused on implementation of pass transistor logic (PTL) methods in the synthesis process of both the diagnostic equipment and the fault-tolerant circuits. The pass transistor logic is usually used for implementing XOR and MUX functions. For example, LUT in FPGA or XOR/XNOR gates in arithmetic logic units can be designed with PTL. We think that PTL method can be used to design novel logic gates with a self-diagnostic function and possibly self-recovery. The brief overview of pass transistor logics will be given in the first section of the paper. The reliability analysis and the examples of logic recovery using PTL are presented in this paper. The PTL designs are represented in digital devices but not for high reliable applications. That is why this subject should be further researched.

3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications

Abstract: We investigate the circuit performance of the junctionless nanowire transistor. We have demonstrated pass transistor-based logic gates using the junctionless transistor. Pass transistor-based basic...

A Power Efficient 500MHz Adder

Abstract: This work presents novel 1-bit full adder and 1-bit half adder circuits. The adders primarily utilize pass transistor logic circuit techniques and achieve full voltage levels for the SUM and CARRY outputs. The 1-bit full adder uses only 16 transistors, and the half adder uses only 15 transistors. They are implemented in 2Snm CMOS technology and are able to achieve a fast delay by limiting the critical path to two stages. Under typical conditions and by using a 10fF load capacitance, the 1-bit full adder achieves a power-delay-product, PDP, of 0. 234fJ for the SUM output signal. This is less than half the PDP of the comparable 28-transistor static CMOS 1-bit full adder. Further, the area of the 1-bit full adder is 0.063 $\mu$m2 and was simulated in HSPICE using a 0.9 V supply voltage. Both the 1-bit full adder and 1-bit half adder circuits were used to build an 8-bit Carry Increment Adder, CIA. The 8-bit CIA adder is functional at 500MHz.

An Energy-Efficient Full-Adder Design Using Pass-Transistor Logic

Abstract: Recently, the data processing capability of the electronic chip is increased significantly. In general data processing means the arithmetic operation on that data. As a result, we have seen that the ALU is present in any data processor. So, the full adder becomes an essential part of the logical and arithmetic unit of the processor. To improve the computational performance of the chip, the improvement of a full adder is necessary. An appropriate logic style helps the designer to design an efficient full adder. In this paper, several logic styles are briefly discussed. We choose to pass transistor logic style to design our new full adder. This logic style is used for reducing power consumption and increasing operational speed. The proposed adder consists of 10 transistors. LTSPICE simulator is used for simulating the schematic. 16nm low power high-k strained silicon transistor model is used for achieving design objectives. A practical transistor model is employed to encounter all practical aspects. The overall performance of the proposed adder circuit is analyzed and compared with conventional circuits.

Low dropout (LDO) voltage regulator with soft-start circuit

Abstract: According to an aspect, a low dropout (LDO) voltage regulator includes a differential amplifier, a pass transistor coupled to an output of the differential amplifier, where the pass transistor is configured to provide an output voltage of the LDO voltage regulator, and a soft-start circuit coupled to the differential amplifier. The soft-start circuit is configured to adjust a soft-start driving signal to control a slope of the output voltage based on the output voltage during a start-up operation of the LDO voltage regulator.

Low dropout regulator (LDO) with frequency-dependent resistance device for pole tracking compensation

Abstract: A system includes a low dropout regulator (LDO) circuit. The LDO circuit includes an error amplifier with an input node, a reference node, and an output node. The LDO circuit also includes a pass transistor with a control terminal, a first current terminal, and a second current terminal. The control terminal is coupled to the output node of the error amplifier, the first current terminal is coupled to a voltage source node, and the second current terminal is coupled to an LDO output node. The LDO output node is coupled to the input node of the error amplifier. The LDO circuit also includes a switched-capacitor network coupled between error amplifier and the pass transistor. The switched-capacitor network comprises a pair of switches and a current-controlled oscillator coupled to control terminals of the switches.

An RFID to I 2 C Bridge IC with Supply Interference Reduction for Flexible RFID Sensor Applications

Abstract: This paper presents a fully passive 13.56MHz RFID to I2C bridge IC, which has been optimized to reduce supply interference, for RFID sensor applications. To reduce the supply interference, this paper proposes a modified low-dropout regulator (LDO) topology. Firstly, the LDO utilizes NMOS as pass transistor to reduce the interference in the main power path. In addition, a charge pump is implemented to increase the supply voltage of the error amplifier, so that the error amplifier is isolated from the supply interference as well. Finally, a bandgap voltage utilizes a low-pass filter so that it carries also minimum interference. In order to support enormous high-precision I2C sensors and eliminate the micro-controller in the application, an I2C master is integrated on-chip directly. This minimizes the complexity of the overall system. This design utilizes an internal volatile memory to exchange the communication information between RFID and I2C. Therefore the RFID and I2C communication operate independently, so that both communications can maintain maximum compatibility and flexibility. The chip is fabricated in a standard 0.35μm CMOS technology and mounted to a tuned RFID transponder coil on an FR4 PCB substrate. Measurements show that the ripple reduction of this proposed LDO reaches 26 dB from 400 Hz to 25MHz in the worst case. During the communication, the ripple of the supply voltage V DDA reaches a maximum 44 mV, while the input ripple of the unregulated DC voltage V DCA reaches maximum 892 mV. The RFID to I2C bridge was employed in a demonstrator for wireless real-time measurement of temperature, humidity, and pressure using two commercially available sensor ICs and two RFID readers.

Methods and apparatuses for multiple-mode low drop out regulators

Abstract: Aspects of the present disclosure generally relate to multi-mode voltage regulators. For example, the regulator may include a first voltage regulator configured to operate in a first power mode. The first voltage regulator is further configured to selectively adjust an output voltage using one of a voltage output of a replica pass transistor of the first voltage regulator or a voltage output of the pass transistor of the first voltage regulator based on a transition from a second power mode to the first power mode.

Single-stage CMOS-based voltage quadrupler circuit

Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level

Voltage regulator with drive voltage dependent on reference voltage

Abstract: A voltage regulator to provide a load current at an output node is presented. The voltage regulator has a pass transistor for providing the load current at the output node from an input node. The voltage regulator contains a driver stage to set a gate voltage at a gate of the pass transistor based on a drive voltage at a gate of a drive transistor. The voltage regulator has voltage regulation means to set the drive voltage in dependence of an indication of the output voltage at the output node and in dependence of a reference voltage for the output voltage. The driver stage has the drive transistor and a diode transistor, wherein the diode transistor forms a current mirror with the pass transistor. The driver stage has a current amplifier amplifies a drive current through the drive transistor to provide an amplified current through the diode transistor.

Design and Implementation of Low Power - High Performance Mixed Logic Line Decoders

Abstract: This paper proposes a mixed logic design technique for implementation of low power - high speed line decoders. Mixed logic design method combines Pass transistor- Dual Value Logic (DVL), Transmission Gate Logic(TGL) and Static CMOS logic. 2–4 decoders are implemented using two novel topologies, a 14-transistor low power topology for reducing power and a 15-transistor high performance topology for minimizing delay and power dissipation with reduced number of transistors in each case. In each case both non-inverting and inverting decoders are implemented, thus providing a total of four new decoder designs. 4–16 decoders are implemented using 2–4 mixed logic pre-decoders and CMOS post-decoder. Mixed logic decoders provide full-swung capability. Furthermore, all the proposed 2–4 decoders are implemented with enable input, this design eliminates the CMOS post decoder and provides a complete mixed logic 4–16 decoder. All the proposed decoders are implemented using Cadence Virtuoso tool in 180nm technology and the simulation results prove that the mixed logic decoders provide a significant improvement in power and delay with reduced number of transistors, outperforming conventional CMOS decoders in almost all cases.

Review on Various Full Adder Circuits

Abstract: This paper explores different Full adder techniques such as Transmission Gate(TG) logic, Complementary pass transistor logic(CPL), Complementary metal oxide semiconductor(CMOS), Gate diffusion input (GDI) and Modified GDI (Gate Diffusion Input) logic. The main objective is find full adders providing low powered and high-speed with good voltage swing. GDI (Gate Diffusion Input) is one of the area effective, high speed and low power technique. It needs smallest amount of transistors as compared to conventional CMOS technology. But the drawback of GDI (Gate Diffusion Input) is that its output has poor logic swing. Modified Gate diffusion technique overcomes this problem.

Anti aging controllable true random number generator for secured AES-based crypto system

Abstract: A tetrahedral oscillator-based true random number generator for secret key generation in cryptosystem has been proposed. The circuit is made to behave correctly for a long time. By applying pass transistors, the aging effects due to hot carrier injection (HCI) and negative bias temperature instability (NBTI) are reduced. This fact is helpful to achieve the goal and its performances have also been improved. Pass transistor makes the transistors to operate only at enabling times. Thus, bit flipping in normal designs are reduced. Due to the complexity in the tetrahedral oscillator hacking will be very tough. The secret key generated from TRNG circuit is adopted in advanced encryption standard (AES) cryptosystem to maintain an off-chip database. Moreover, controlling circuits for TRNG have been introduced because in any of the cryptosystem man-in-middle attack is possible. To avoid this controlling circuits are used to identify the authenticity of customers. Simulation results explain that our aging resistant design can be used for generating more reliable keys. Although the operating conditions changes, the DC operating point of the system does not change more. The randomness is also shown through NIST tests.

Performance Analysis of Adder Architecture using Modified Pass transistor Adiabatic Logic Circuits

Abstract: This article analyses the prominence of modified pass transistor adiabatic logic circuits, such as IPAL and EEPAL. Both these logic circuits are operated by four phase trapezoidal power clock source and these employ optimal number of devices in it. Conventional MOSFET devices suffer from short channel effects the as device size scales down to lower technology nodes. FinFET acts as a promising device which can overcome the limitations of MOSFET. The FinFET based quasi-adiabatic logic circuits operating using four phase power clock supplies, namely, 2N2P, 2N2N2P, PFAL, EEPAL and IPAL structures have been considered for the analysis. All the circuits have been designed using FinFET 32nm technology in Cadence® Virtuoso EDA tool environment and the results authenticate the improved energy efficiency features of EEPAL and IPAL.

MOSFET-like Carbon nanotube Field Effect Transistor based Full adder design

Abstract: CMOS transistor of the commercial chip is currently at 7nm technology node. Fabrication engineer is now facing some complexities to further scale down the size of the transistor. Quantum mechanical phenomenon is occurred and significantly worsens the performance as well as it changes the overall properties of the transistor. So, researchers have developed several types of devices in order to overcome the shortcomings of CMOS. One of the devices is the Carbon nanotube Field Effect Transistor (CNFET). It is a suitable device because it can be scaled down up to 2nm and it overcome some limitations. One of the major advantages of CNFET is that the carrier faces theoretically zero resistance when passing through the carbon nanotube because that tube acts as a channel analogous to E-MOS. In this research, a new adder circuit is designed using 32nm CNFET model. The proposed circuit is based on Pass Transistor Logic (PTL) in order to reduce the number of transistors and silicon area. A comparative study is conducted by simulation. The results concluded that the proposed circuit performs better than other conventional adders in terms of power consumption and time delay.

Low dropout regulator with a controlled startup

Abstract: A low dropout voltage regulator incorporates an N-channel MOS pass transistor, a main error amplifier, a first buffer circuit, an auxiliary error amplifier, a second buffer circuit, and a decision circuit. The auxiliary error amplifier consumes less bias current. In one embodiment, the decision circuit compares the portion of the output voltage with a bias voltage to control the gate of the N-channel MOS pass transistor, wherein the value of the bias voltage is less than the value of the reference voltage.