Showing papers on "Pass transistor logic published in 2020"

Design of a Two-Bit Magnitude Comparator Based on Pass Transistor, Transmission Gate and Conventional Static CMOS Logic

Abstract: Since there is a swift technological progress going on in the recent years, semiconductor industry evolved to such an extend that requirement of optimal performance in electronic circuits have become essential. Therefore, there is high requirement of energy efficient fast circuit designs in modern Integrated Circuits (IC). Comparison of two binary digits is one of the fundamental arithmetic operations in Arithmetic Logic Units (ALU) of ICs and processors. A hybrid design approach for implementing a two-bit Magnitude Comparator (MC) has been proposed in this work. The hybrid design consists of three different logic techniques namely: (a) Pass Transistor Logic (PTL), (b) Transmission Gate Logic (TGL) and (c) Conventional Static CMOS Logic (C-CMOS logic). The effectiveness of the proposed design has been compared with 6 state of art two-bit magnitude comparators using Cadence tools in 90 nm technology node. The proposed design showed best perormacne in case of delay and Power Delay Product (PDP) which proved the effectiveness of the design, Moreover, power consumption of the design is also low which makes it highly usable for portable devices that requires low-power consumption.

Performance Analysis of FinFET based 2:1 Multiplexers for Low Power Application

Abstract: In this paper, a comparison is made between FINFET based Gate Diffusion Input (GDI) and Pass Transistor (PT) based 2:1 Multiplexers in terms of delay, average power dissipation, and Power delay product (PDP). Both the multiplexers are designed using an 18nm technology node and functional at 0.8V supply voltage. GDI based mux consumes very less power dissipation of 46.69nW, which is 46.04% lesser than the PT based Mux. If the user requirement is of fast operation than GDI based Mux meets the criteria. It takes 2.11ps to pass the signal at the output, which is 4.3 times faster than PT based Mux. PDP of GDI and PT based Mux is 0.143aJ and 0.755aJ. Additionally, GDI based Mux demonstrates better performance with 3.15nW power dissipation. The multiplexers can be used in many combinational circuits, therefore, if the performance of the multiplexer is improved, the complete circuit is bound to give better performance.

A Unique Design of Hybrid Full Adder for the Application of Low Power VLSI Circuits

Abstract: In this research work, a unique Hybrid Full Adder (HFA) is developed by deploying Pass Transistor Logic (PTL), CMOS logic and transmission gate (TG) logic on the Cadence Virtuoso platform in 90-nm technology. Various modules, namely the XOR module, the carry generator module, sum generator module are implemented for realizing 1-bit HFA. An inverter logic is employed next to the XOR logic to obtain the logic of XNOR which is required for designing the proposed HFA. The propagation delay (t pd ) and average power of the circuit are turned out to be 20 ns and ~6.889 μW respectively, at 1V supply voltage. So, the power delay product (PDP) is remarkably low with the value 137.78 fJ of the proposed HFA. The area is also satisfyingly less because the proposed design used only 13 transistors. Hence, the proposed design gives a remarkable improvement in terms of PDP which may be applicable for basic building blocks of VLSI circuits.

Novel Low-Complexity and Low-Power Flip-Flop Design

Abstract: In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering

Abstract: Securing the intellectual property (IP) from counterfeiting is an important goal toward trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an adversary from de-layering the chip and stealing IP. In this paper, we propose threshold voltage modulation to realize 2-input static camouflaged logic that can hide six functionalities. We extend the concept of threshold-voltage defined logic to propose multi-input camouflaged gates capable of hiding six 3-input Boolean functions (NAND, NOR, AOI, OAI, XOR, and XNOR). We also propose interconnect camouflaging technique which hides the original connectivity of nets using a novel threshold-voltage defined pass transistor mux. Since threshold voltages are asserted during fabrication and are difficult to identify during optical reverse engineering (RE)-based techniques, the adversary will be forced to launch a brute-force search. We present a thorough analysis of RE effort and overheads associated with the proposed camouflaging techniques. The proposed methodology is demonstrated using fabricated test-chip in 65 nm technology.

Modeling and Analysis of On-Chip Power Noise Induced by an On-Chip Linear Voltage Regulator Module With a High-Speed Output Buffer

Abstract: In this paper, analytical models of on-chip power noise induced by an on-chip linear voltage regulator module (VRM) circuit with a high-speed output buffer are proposed. Based on the piecewise linear approximated mosfet I – V curve model, closed-form equations for the on-chip power noise induced by an on-chip low-dropout regulator are derived. The accuracy of the proposed analytical model is validated by SPICE simulation with a 110-nm CMOS technology library. Based on the proposed analytical models, the impacts of VRM design parameters on VRM output noise induced by load current and external noises are analyzed. Because self-impedance at the VRM output and external noise transfer functions share a common resonant frequency, the on-chip power noise is minimized by avoiding the resonant frequency from peak frequencies of noise source spectrums. The larger on-chip decoupling capacitance at load reduces, the overall on-chip VRM output noise. While the larger pass transistor size reduces the on-chip VRM output noise induced by the reference voltage fluctuation, it increases the noise generated by off-chip power fluctuation. The reference voltage node needs to be carefully designed, as opposed to an off-chip power distribution network, due to its dominant impact on the on-chip VRM output noise. The analysis results based on the proposed model provide an in-depth understanding of and useful design guidance for on-chip power noise induced by the on-chip linear VRM with a high-speed output buffer.

Electronics: from Classical to Quantum

Abstract: This book gives clear explanations of the technical aspects of electronics engineering from basic classical device formulations to the use of nanotechnology to develop efficient quantum electronic systems. As well as being up to date, this book provides a broader range of topics than found in many other electronics books. This book is written in a clear, accessible style and covers topics in a comprehensive manner. This book’s approach is strongly application-based with key mathematical techniques introduced, helpful examples used to illustrate the design procedures, and case studies provided where appropriate. By including the fundamentals as well as more advanced techniques, the author has produced an up-to-date reference that meets the requirements of electronics and communications students and professional engineers. Features Discusses formulation and classification of integrated circuits Develops a hierarchical structure of functional logic blocks to build more complex digital logic circuits Outlines the structure of transistors (bipolar, JFET, MOSFET or MOS, CMOS), their processing techniques, their arrangement forming logic gates and digital circuits, optimal pass transistor stages of buffered chain, sources and types of noise, and performance of designed circuits under noisy conditions Explains data conversion processes, choice of the converter types, and inherent errors Describes electronic properties of nanomaterials, the crystallites’ size reduction effect, and the principles of nanoscale structure fabrication Outlines the principles of quantum electronics leading to the development of lasers, masers, reversible quantum gates, and circuits and applications of quantum cells and fabrication methods, including self-assembly (quantum-dot cellular automata) and tunneling (superconducting circuits), and describes quantum error-correction techniques Problems are provided at the end of each chapter to challenge the reader’s understanding

A Fully Integrated High-Power-Supply-Rejection Linear Regulator With an Output-Supplied Voltage Reference

Abstract: This study proposes an output capacitor-less linear regulator with high power supply rejection (PSR) for a wireless power transmission system. To achieve high PSR with a noisy input voltage, a fully integrated linear regulator with its reference circuit supplied by the output voltage is proposed. The proposed technique can isolate the reference circuit from the noisy $\text{V}_{IN}$ , thereby reducing the requirements of the conventional bulky low-pass filter loading the reference voltage node while achieving superior PSR performance. The regulator uses an N-type pass transistor and a dual-feedback structure to achieve wideband ripple-filtering and fast transient responses. The proposed regulator is compatible with typical biomedical implants requiring a 10mA load current at 1.1V output voltage while consuming a total quiescent current of $276~\mu $ A. A PSR performance was measured to be −48 and −56 dB against the $\text{V}_{IN}$ and charge pump at 10 MHz, respectively. The unity gain bandwidth (UGB) of the regulator was 291MHz. The proposed regulator was fabricated using commercial TSMC 0.18- $\mu \text{m}$ CMOS technology with an area of 0.1054 mm2 including the reference circuit.

High-PSR Capacitorless LDO with Adaptive Circuit for Varying Loads

Abstract: A capacitorless low-drop-out (LDO) regulator with an NMOS pass transistor-based adaptive network to achieve high and constant power-supply rejection (PSR) for varying loads is presented. The propos...

VLSI Architecture for High Performance Wallace Tree Encoder

Abstract: In the research, the VLSI architecture design for Wallace tree encoder with modified full adder is proposed. In analog to digital conversion process, Wallace tree encoder is utilized in the process of converting the thermometer code to binary. This can be termed to be a high speed application and a flash type of flash ADC, which is a resistor ladder, encoder and comparator circuit. A suitable encoder is required for getting binary code from comparator output. Reducing energy of the encoder is a vital concern whereas designing the minimal power flash form ADC. Wallace tree encoders diminishes the mistake due to the availability of zeroes in the sequence of the once presence to the series of zeroes in a comparator output, but it consumes more power. Hence in the proposed work, a low power Wallace tree encoder is designed using pass transistor logic (PTL) full adder. The proposed design dissipates only 74.15nW power and delay also reduced to 0.0495ns. The circuit is designed using CADENCE 5.1.0 EDA equipped and simulated with the application of spectre virtuoso.

Mathematical analysis of organic-pass transistor using pseudo-p-OTFTs

Abstract: Steady state behavior analysis of organic thin film transistor (OTFTs) has been thoroughly researched in the past few decades. Yet, this static logic analysis has drawbacks of high power dissipation and high power consumption, and a large number of prerequisites in the number of transistors for the digital logic circuit application. Hence, to overcome these basic fundamental drawbacks of static logic, the dynamic logic study of organic thin film transistor has been analyzed in this paper. The fundamental basic of dynamic logic is a pass transistor for which logic high and logic low model is designed at an operating voltage of 5 V and frequency of 5 kHz. Additionally, the novel approach of analytical model for organic pass transistor (OPT) circuit is included and verified using MATLAB. The transient individualities of organic pass transistor OPT are examined through Atlas 2-D numerical device simulator. The reduction in the power dissipation along with additional voltage scaling and reduction in the clock frequency such as pipelining may further enable the applications into more complex VLSI ICs.

Design of LFSR Circuit based on High Performance XOR gate

Abstract: In the proposed work, we focused on MCML (MOS current mode logic), dynamic current logic and PTL (pass transistor logic) based XOR circuit and see the impact on LFSR (linear feedback shift register) Evaluate the performance parameter in terms of power dissipation and critical path delay Also compare and contrast with previous literature The circuit implementation of 3, 4 and 5-bit LFSR circuit is built by Verilog HDL code and synthesis is carried out using 90nm CMOS technology (GPDK) on Cadence tool

Design of a High-Performance 2-bit Magnitude Comparator Using Hybrid Logic Style

Abstract: Design of a 2-bit binary Magnitude Comparator (MC) is presented in this research. The proposed MC has been designed using Conventional CMOS (CCMOS) logic, Pass Transistor Logic (PTL). The design is simulated along with 5 other existing MC designs in order to carry out evaluation and comparison. The proposed 2-bit MC displayed satisfactory level of improvement in speed and power. For this reason, significant enhancement in Power Delay Product (PDP) could have been attained. Due to the significant enhancement in performance, the proposed MC can be considered as a highly effective alternative to the existing MC designs.

A comparative study on the effects of technology nodes and logic styles for low power high speed VLSI applications

Abstract: Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

Semiconductor memry device

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a memory structure and a logic structure. The memory structure includes memory cells connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and may include a first plane and a second plane arranged in the first direction. The logic structure may be disposed between a substrate and the memory structure and may include a row decoder. The row decoder may include: a pass transistor circuit commonly connected to the first plane and the second plane; and a block switch circuit controlling the pass transistor circuit. The block switch circuit may be disposed on a first plane area and a second plane area of the logic structure overlapping the first plane and the second plane in a third direction vertical to the first direction and the second direction. The pass transistor circuit may be disposed on an interval area between the first plane area and the second plane area. The present invention disposes the two planes to share one row decoder, thereby reducing an occupation area of the row decoder to enhance the integration density.

Design of Pass Transistor based Phase Frequency Detector for Fast Frequency Acquisition Phase Locked Loop

Abstract: This paper presents the modified design of the pass transistor-based PFD with improved output characteristics for phase locked loop. The proposed design modifies the reset approach which improves the speed of the PFD to 3.3GHz. Here, the number of transistors has been reduced which adds the advantage of low power consumption. The power consumption achieved as 253.5µw at 3.3GHz reference frequency. The design is based on cadence 0.18 µm CMOS process with the supply voltage of 1.8 V. The design is used for low power and high-speed application.

Design and Analysis of PTL based Basic gates and Adder with Improved Performance

Abstract: The advancement of portable electronic devices leads to the requirement of digital circuits which are fast, small in size and consume minimal powerHigh speed addition has always been a primary requirement for high-performance processorsConventionally, CMOS logic is used to design adder topologies but as the transistor count decreases the threshold loss problems seem to creep in To eliminate this problem, optimized values of aspect ratios (W/L) with body bias voltage are choosen and a suitable combination is selected to design 2T AND, 2T OR and 3T XOR cells based on the Pass Transistor Logic (PTL)The modified area efficient PTL structures give better performance in terms of speed with a reasonable threshold loss The design is carried out in Cadence Virtuoso tool for 180nmFurther, 3T XOR and 8T FA and circuits have been designed and analyzed in 45nm technologyPTL based designs in 45nm with proper body bias voltage are showing improved results in terms of power, speed, area and giving strong 1(0994V) and strong 0(0V) values with reduction in threshold loss Finally, a comparative study is also made with the fast adder circuits already available in the literature

Low dropout regulator with smart offset

Abstract: A low-dropout (LDO) regulator. The LDO regulator includes a pass transistor, a charge pump connected to the pass transistor, and an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO, wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor.

Adaptive gate-biased field effect transistor for low-dropout regulator

Abstract: A load circuit of a low-dropout (LDO) regulator is disclosed herein according to certain aspects. The load circuit includes a field effect transistor having a source coupled to a supply rail, a gate, and a drain coupled to a gate of a pass transistor of the LDO regulator. The load circuit also includes an adjustable voltage source coupled between the drain and the gate of the field effect transistor, and a voltage control circuit configured to detect a change in a current load through the pass transistor, and to adjust a voltage of the adjustable voltage source based on the detected change in the current load.

Coupling Noise Mitigation using a Pass Transistor

Abstract: Due to scaling effects, integrated circuits are becoming increasingly more sensitive to noise and delay effects caused by interconnect coupling. Coupling noise has now become a critical design and verification issue in DSM designs. Although driver sizing is a practical and a feasible technique for controlling the crosstalk noise in the post route design stage, it may create additional crosstalk issues with neighboring wires. Furthermore, a sized up gate may result may affect the timing of paths through the gate. This work proposes a new coupling noise mitigation methodology based on a new pass transistor design. This approach results in smaller area overhead compared to driver sizing taken alone and requires minimum change in circuit layout. Results show a 41% area savings compared to victim driver sizing method taken alone for all cases considered.

High PSR output-capacitor-less LDO with double buffers technique

Abstract: An output-capacitorless LDO regulator with double buffers technique has been proposed and simulated in a commercial 0.18µm CMOS process in this paper. To get over the tradeoff between PSR against other important design parameters such as loop stability and load capability, the proposed LDO replicates a supply ripple to the gate of pass transistor using a PMOS buffer with diode connected transistor and extends the load range by an NMOS buffer. Simulation results verify that PSR is improved effectively in the whole unity gain frequency (UGF) and the improvement is up to 40dB. In addition, the quiescent current is 33µA, providing a maximum load current of 50 mA. Besides, excellent load regulation of 2µ V/mA and line regulation of 0.06mV/V are obtained with supply from 1.2V to 2V.

Method and system for buck converter current re-use for minimum switching frequency pulse-skip operation

Abstract: A buck voltage converter comprising a high side switch, a low side switch, a capacitor, an inductor, a gate driver circuit having outputs coupled to the gate terminal of the high side switch and the gate terminal of the low side switch, and a separate voltage regulator circuit that powers circuitry internal to the buck voltage converter. The voltage regulator circuit includes a multiplexer having a first multiplexer input coupled to the input voltage source, a second multiplexer input coupled to the buck output of the buck voltage converter, and one or more multiplexer control inputs to select which of the two multiplexer inputs is coupled to a multiplexer output and pass transistor having a first terminal coupled to the multiplexer output of the multiplexer and having a second terminal coupled to the regulator output of the voltage regulator.

Hybrid Pass Transistor Logic with Ambipolar Transistors

Abstract: In comparison to the conventional complementary pull-up and pull-down logic structure, the pass transistor logic (PTL) family reduces the number of transistors required to perform logic functions, thereby reducing both area and power consumption. However, this logic family requires inter-stage inverters to ensure signal integrity in cascaded logic circuits, and inverters must be used to provide each logical input signal in its complementary form. These inverters and complementary signals increase the device count and significantly degrade overall system efficiency. Dual-gate ambipolar field-effect transistors natively provide a single-transistor XNOR operation and permit highly-efficient and compact circuits due to their ambipolar capabilities. Similar to PTL, logic circuits based on ambipolar field-effect transistors require complementary signals. Therefore, numerous inverters are required, with significant energy and area costs. Ambipolar field-effect transistors are a natural match for PTL, as hybrid ambipolar-PTL circuits can simultaneously use these inverters to satisfy their necessity in both PTL and ambipolar circuits. We therefore propose a new hybrid ambipolar-PTL logic family that exploits the compact logic of PTL and the ambipolar capabilities of ambipolar field-effect transistors. Novel hybrid ambipolar-PTL circuits were designed and simulated in SPICE, demonstrating strong signal integrity along with the efficiency advantages of using the required inverters to simultaneously satisfy the requirements of PTL and ambipolar circuits. In comparison to the ambipolar field-effect transistors in the conventional CMOS logic structure, our hybrid full adder circuit can reduce propagation delay by 47%, energy consumption by 88%, energy-delay product by a factor of 9, and area-energy-delay product by a factor of 20.

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance

Abstract: In the past, Pass Transistor Logic (PTL) was widely used due to benefits in terms of speed and power consumption coming from the reduced number of transistors. However, issues such as threshold drop across the single-channel pass transistors and high sensitivity to process variations have prevented the use of PTL in advanced nanometer technologies. In this paper, we propose a novel logic family named Dual Mode Pass Logic (DMPL), which allows for high speed and low power consumption while maintaining robustness down to the sub-threshold voltage region. The DMPL effectively combines PTL to reduce energy and power consumption along with the flexibility of Dual Mode Logic (DML) to switch to a speed improved operating mode according to the system requirement. Simulation analysis performed on basic NOR/NAND gates implemented in 16 nm Finfet technology demonstrates that DMPL can reduce energy and power by 33% and 42% as compared to logically equivalent static CMOS design. Moreover, running frequency of a DMPL circuit can exceed that of its static CMOS counterpart by 84% when speed is mandatory. Additionally, DMPL gates demonstrate similar robustness as static CMOS implementations under process and temperature variations at lower supply voltages.

Design a 4-Bit Carry Look-Ahead Adder Using Pass Transistor for Less Power Consumption and Maximization of Speed

Abstract: A high-speed power-efficient 4-bit carry look-ahead adder (CLA) is designed by using pass transistor logic (PTL). To overcome the issues of delay as well as power consumption, the PTL has been deliberately used in integrated circuits design. The pass transistor logic is a better way to implement circuits for high-speed and low-power applications in less number of transistors. Parameters like delay, power consumption, and energy are reduced so much as compared to available logic styles such as static CMOS logic, DOMINO logic, and sub-threshold regime logic. All the analysis and simulations have been done by Cadence Virtuoso simulation tool in 180 nm technology with the supply voltage of 1.8 V at 5 MHz operating frequency.

Hybrid Pass Transistor Logic with Dual-Gate Ambipolar CNTFETs

Abstract: Pass Transistor Logic (PTL) provides decreased device count relative to conventional complementary circuit structures, but the buffering inverters required for cascading PTL gates diminishes this advantage. Dual-gate ambipolar carbon nanotube transistors (DG-A-CNTFETs) are a natural match for PTL due to the fact that both require significant use of inverters between logic stages. This work therefore proposes a hybrid PTL structure with DG-A-CNTFETs that exploits the compact logic of PTL in concert with the native XNOR gates with DG-A-CNTFETs. A novel hybrid PTL DG-A-CNTFET full adder is proposed as an example of this novel logic concept, and simulation results demonstrate superior performance with a 43% reduction in device count relative to conventional complementary circuit design with DG-A-CNTFETs.

Design of full adder circuit with minimum transistors

Abstract: Full adders are the most important building blocks in digital design that not only perform additional operations but also help in calculating several other functions such as subtraction, multiplication and division operations. In VLSI technology, different types of adders are often essential depending on the requirements in processors to ASCIs. We found in the latest research that the pass transistor logic consumes less power than the CMOS. This paper includes an optimized full adder circuit survey with a minimum number of transistors. We have also derived an optimal full adder circuit that is implemented for simulation and the findings will be addressed further.

Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection During System-Level ESD

Abstract: This work studies the effect of system-level ESD on chip-level power integrity of ICs The analysis reveals that isolating the ground nets of the various on-chip power domains impedes the cross-domain propagation of ESD-induced supply noise Further analysis as well as circuit simulation show that an integrated voltage regulator (IVR) can provide increased immunity to ESD-induced supply noise, especially if the internally generated power supply does not utilize any PCB-level decoupling capacitors However, the IVR’s PMOS pass transistor may discharge the internally regulated supply if the IO supply domain collapses due to ESD Key findings of the analysis are confirmed by measurements performed on two test chips which have differing IVR designs

Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms

Abstract: Conventional static CMOS design employing pull-up and pull-down network for implementing logic functions has been one of the most reliable and widely used design techniques over the years. However, high input impedance and transistor count remains a major problem which result in high silicon area, high power consumption and increased delay. This research focus on reducing power, delay and transistor count in Conventional Static CMOS based 4-bit Carry Look Ahead adder. The conventional static CMOS XOR and gates are replaced by Gate Diffusion Input technique and Pass Transistor logic based XOR and AND gates in the input side to enhance performance parameters and to reduce transistor count. Two new modified CLA adder have been proposed and their performance parameters have been compared with conventional circuit using Cadence simulation tools. The proposed designs showed significant performance improvement while keeping the advantages of static CMOS Logic.