Topic
Petri net
About: Petri net is a research topic. Over the lifetime, 25039 publications have been published within this topic receiving 406994 citations.
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06 Mar 2006
TL;DR: This paper presents an effective approach to formally verify SystemC designs into a Petri-Net based representation, which is particularly suitable for models at a high level of abstraction, such as transaction-level.
Abstract: This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed formal verification SystemC designs Petri-net model model checking timed temporal logic . The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments
89 citations
TL;DR: The design and prototype implementation of a Grid workflow management system is presented, including a set of description languages required for orchestrating abstract workflows and for mapping them onto real Grid infrastructure, as well as a workflow enactment service that executes loosely coupled Grid jobs on the Grid.
89 citations
TL;DR: This paper proposes a new concept called characteristic implicit resource-transition nets, and successfully establishes a necessary and sufficient condition for a resource subset to generate an SMS.
Abstract: Systems of sequential systems with shared resources (S4PR) represent a class of Petri nets that have powerful modeling capability for resource allocation systems. Their efficient siphon computation is important. An open issue is how to determine whether a resource subset can generate a strict minimal siphon (SMS). This paper presents the answer. In particular, we propose a new concept called characteristic implicit resource-transition nets. By charactering such nets, we successfully establish a necessary and sufficient condition for a resource subset to generate an SMS.
89 citations
16 Oct 2006
TL;DR: A novel approach to reason about soundness based on so-called causal footprints is presented, which proves that the "vicious circle", that is heavily discussed in EPC literature, is unsound.
Abstract: The correctness of business process models is of paramount importance for the application on an enterprise level. A severe problem is that several languages for business process modelling do not have formal execution semantics which is a prerequisite to check correctness criteria. In this context, soundness defines a minimum correctness criterion that a process model should fulfill. In this paper we present a novel approach to reason about soundness based on so-called causal footprints. A causal footprint represents a set of conditions on the order of activities that holds for every case of a process model. We identify three kinds of error patterns that affect the soundness of a process model, namely the deadlock pattern, the multiple termination pattern, and the trap pattern. We use Eventdriven Process Chains (EPCs) and Petri nets to demonstrate the applicability of our approach for both conceptual as for formal process modelling languages. Furthermore, it can easily be applied to other languages, such as UML activity diagrams or BPEL. Based on the trap pattern, we prove that the .vicious circle., that is heavily discussed in EPC literature, is unsound.
89 citations
TL;DR: Control logic synthesis taking into account the graphical representation of CtlSM's and the distributed state representation in terms of markings is proposed and justified and two examples-the cat-and-mouse game and a model of a metro line-illustrate the theoretical results.
Abstract: This paper treats the forbidden state problem for the class of discrete-event dynamical systems (DEDS's) which can be modeled as controlled state machines (CtlSM's). CtlSM's constitute a special class of controlled Petri nets (CtlPN's) where no synchronization requirements are included in the system model. Synchronization and other safety requirements are modeled via sets of forbidden states. In this paper we study methods guaranteeing these constraints by disabling some of the controllable transitions. We assume that the full state is observable. Control logic synthesis taking into account the graphical representation of CtlSM's and the distributed state representation in terms of markings is proposed and justified. Two examples-the cat-and-mouse game and a model of a metro line-illustrate the theoretical results. >
89 citations