Phase detector characteristic

About: Phase detector characteristic is a research topic. Over the lifetime, 1627 publications have been published within this topic receiving 17008 citations.

A New Single-Phase PLL Structure Based on Second Order Generalized Integrator

Abstract: Phase, amplitude and frequency of the utility voltage are critical information for the operation of the grid-connected inverter systems. In such applications, an accurate and fast detection of the phase angle, amplotude and frequency of the utility voltage is essential to assure the correct generation of the reference signals and to cope with the new upcoming standards. This paper presents a new phase-locked-loop (PLL) method for single-phase systems. The novelty consists in generating the orthogonal voltage system using a structure based on second order generalized integrator (SOGI). The proposed structure has the following advantages: — it has a simple implementation; — the generated orthogonal system is filtered without delay by the same structure due to its resonance at the fundamental frequency, — the proposed structure is not affected by the frequency changes. The solutions for the discrete implementation of the new proposed structure are also presented. Experimental results validate the effectiveness of the proposed method.

Phase modulated system with phase domain filtering

Abstract: A phase modulation system includes a phase mapping circuit (218) for mapping binary data into a plurality of discrete phase values in accordance with a predetermined phase modulation scheme. The discrete phase values are then filtered in the phase domain by a filter (220) to provide a filtered output. This filtered output is then digitized and input to a numerically controlled oscillator for phase modulating a carrier.

Film source video detection

Abstract: A television line doubler (interlaced to progressive scan converter) incorporating the following aspects—an improved field motion detector which does not treat low frequency vertical transitions as motion; a frame motion detector having an improved ability to differentiate motion from subcarrier signal components; a sawtooth artifact detector; a sawtooth artifact detector in combination with a film pattern detector, such that the artifact detector can take the film pattern detector out of film mode earlier than it would if it only were responsive to a break in the film pattern; tandem field motion detectors; an improved field based film detector; film pattern detectors and motion detectors used therewith which operate by performing end-of-field calculations; the combination of a field motion detector and a frame motion detector such that the frame motion detector provides a motion signal used as a verification by the field motion detector; an improved NTSC film detector requiring a minimum number of NTSC film pattern sequences; and an improved PAL film detector employing a minimum motion threshold detector.

Phase locked loop (PLL) with linear parallel sampling phase detector

Abstract: A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective "window" signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

A simple precharged CMOS phase frequency detector

Abstract: We propose a simple precharged CMOS phase frequency detector (PFD). The circuit uses 18 transistors and has a simple topology. Therefore, the detector, in a 0.8-/spl mu/m CMOS process, works up to clock frequencies of 800 MHz according to SPICE simulations on extracted layout. Further, the detector has no dead-zone in the phase characteristic which is important in low jitter applications. The phase and frequency characteristics are presented and comparisons are made to other PFDs. The phase offset of the detector is sensitive to differences of the duty-cycle between the inputs. Mixed-mode simulations are presented of the lock-in procedure for a phase-locked loop (PLL) where the detector is used. Measurements on the detector are presented for a test-chip with a delay-locked loop (DLL) where the phase detection ability of the detector has been verified.