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Phase frequency detector

About: Phase frequency detector is a research topic. Over the lifetime, 1684 publications have been published within this topic receiving 16654 citations.


Papers
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Proceedings ArticleDOI
18 Jun 2006
TL;DR: In this article, a phase-locked-loop (PLL) method for single-phase systems was proposed to detect the phase angle, amplitude and frequency of the utility voltage.
Abstract: Phase, amplitude and frequency of the utility voltage are critical information for the operation of the grid-connected inverter systems. In such applications, an accurate and fast detection of the phase angle, amplotude and frequency of the utility voltage is essential to assure the correct generation of the reference signals and to cope with the new upcoming standards. This paper presents a new phase-locked-loop (PLL) method for single-phase systems. The novelty consists in generating the orthogonal voltage system using a structure based on second order generalized integrator (SOGI). The proposed structure has the following advantages: — it has a simple implementation; — the generated orthogonal system is filtered without delay by the same structure due to its resonance at the fundamental frequency, — the proposed structure is not affected by the frequency changes. The solutions for the discrete implementation of the new proposed structure are also presented. Experimental results validate the effectiveness of the proposed method.

1,023 citations

Journal ArticleDOI
TL;DR: This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.
Abstract: Phase/frequency detectors deliver output in the form of three-state, digital logic. Charge pumps are utilized to convert the timed logic levels into analog quantities for controlling the locked oscillators. This paper analyzes typical charge-pump circuits, identifies salient features, and provides equations and graphs for the design engineer.

894 citations

Journal ArticleDOI
TL;DR: A dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2/spl pi/) phase shift, and large operating range, and the design of an experimental prototype in 0.8-/spl mu/m CMOS technology is described.
Abstract: This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2/spl pi/) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-/spl mu/m CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV.

486 citations

Journal ArticleDOI
TL;DR: In this article, the phase-domain phase-locked loops (PLLs) are replaced by a time-to-digital converter and a simple digital loop filter, and the measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications.
Abstract: A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls. When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump-based phase-locked loops (PLLs), since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. An actual implementation of an all-digital PLL (ADPLL)-based local oscillator and transmitter used in a commercial 0.13-/spl mu/m CMOS single-chip Bluetooth radio has recently been disclosed. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. Due to the lack of the correlational phase detection mechanism, the loop does not contribute to the reference spurs. The measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications. In this paper, we present the mathematical description and operational details of the phase-domain ADPLL.

215 citations

Journal ArticleDOI
TL;DR: In this paper, a 10-Gb/s phase-locked clock and data recovery circuit incorporating a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming is presented.
Abstract: A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.

185 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202226
202121
202060
201976
201880