Showing papers on "Phase noise published in 2000"

Phase noise in oscillators: a unifying theory and numerical methods for characterization

Abstract: Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterization. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterization of timing jitter and spectral dispersion, for computing of which we have developed efficient numerical methods. We demonstrate our techniques on a variety of practical electrical oscillators and obtain good matches with measurements, even at frequencies close to the carrier, where previous techniques break down. Our methods are more than three orders of magnitude faster than the brute-force Monte Carlo approach, which is the only previously available technique that can predict phase noise correctly.

Noise in RF-CMOS mixers: a simple physical model

Abstract: Flicker noise in the mixer of a zero- or low-intermediate frequency (IF) wireless receiver can compromise overall receiver sensitivity. A qualitative physical model has been developed to explain the mechanisms responsible for flicker noise in mixers. The model simply explains how frequency translations take place within a mixer. Although developed to explain flicker noise, the model predicts white noise as well. Simple equations are derived to estimate the flicker and white noise at the output of a switching active mixer. Measurements and simulations validate the accuracy of the predictions, and the dependence of mixer noise on local oscillator (LO) amplitude and other circuit parameters.

Physical processes of phase noise in differential LC oscillators

Abstract: There is an unprecedented interest among circuit designers today to obtain insight into the mechanisms of phase noise in LC oscillators. For only with this insight is it possible to optimize oscillator circuits using low-quality integrated resonators to comply with the exacting phase noise specifications of modern wireless systems. In this paper we concentrate on an understanding of the popular differential LC oscillator. We introduce simple models to capture the nonlinear processes that convert voltage or current thermal noise in resistors or transistors into phase noise in the oscillator. The analysis does not require hypothetical elements, such as limiters or amplitude control loops, to fully explain phase noise. A simple expression at the end accurately specifies thermally induced phase noise, and lends substance to Leeson's original hypothesis. Next, the upconversion of flicker noise into phase noise is traced to mechanisms first identified in the 1930's, but apparently since forgotten. Unlike thermally induced phase noise, which appears as phase modulation sidebands, flicker noise is shown to upconvert by bias-dependent frequency modulation. The results are validated against SpectreRF simulations and measurements on two differential CMOS oscillators tuned by resonators with very different Q's.

Multiloop optoelectronic oscillator

Abstract: We describe and demonstrate a multiloop technique for single-mode selection in an optoelectronic oscillator (OEO). We present experimental results of a dual loop OEO, free running at 10 GHz, that has the lowest phase noise (-140 dBc/Hz at 10 kHz from carrier) of all free-running room-temperature oscillators to date. Finally, we demonstrate the first fiber-optic implementation of the carrier suppression technique to further reduce the close-to-carrier phase noise of the oscillator by at least 20 dB.

Reducing MOSFET 1/f noise and power consumption by switched biasing

Abstract: Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 /spl mu/m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%.

A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver

Abstract: A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc.

A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications

Abstract: One approach to implementation of low-phase-noise integrated fixed-frequency local oscillators (LOs) for use as the RF LO in a blockdown-convert receiver architecture for PCS wireless communications down-converts the entire RF band to a lower frequency using a fixed-frequency LO. This allows new approaches to the implementation of low-phase-noise oscillators with low-Q components. The technique uses a DLL-based frequency multiplier to synthesize a RF LO whose phase noise is closely related to that of the reference crystal and not dependent on the phase noise of a VCO. An experimental prototype generates a 900 MHz signal and is designed to meet the requirements of the IS-137 standard. The device achieves a phase noise of -123dBc/Hz at a 60 kHz offset frequency with 39 mA overall current consumption from a 3.3 V supply. This prototype was fabricated in 0.35 /spl mu/m double-poly five-metal CMOS.

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator

Abstract: Fractional-N frequency synthesis based on /spl Delta//spl Sigma/ modulators offers wide bandwidth with narrow channel spacing and alleviates PLL design constraints for phase noise and reference spur. However, the synthesizer phase noise performance is significantly affected by the high-frequency out-of-band noise, which is difficult to suppress with the finite number of PLL loop filter poles. This work uses a 3b 3rd-order modulator that generates less high-frequency noise and makes the system less sensitive to the phase detector nonlinearity.

Coupled optoelectronic oscillators for generating both RF signal and optical pulses

Abstract: We present experimental results of coupled optoelectronic oscillators (COEO) constructed with a semiconductor optical amplifier-based ring laser and a semiconductor colliding pulse mode-locked laser. Each COEO can simultaneously generate short optical pulses and spectrally pure radio frequency (RF) signals. With these devices, we obtained optical pulses as short as 6.2 ps and RF signals as high, in frequency, as 18.2 GHz with a spectral purity comparable with an HP83731B synthesizer. These experiments demonstrate that COEO's are promising compact sources for generating low jitter optical pulses and low phase noise RF/millimeter wave signals.

A CMOS self-calibrating frequency synthesizer

Abstract: A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain K/sub o/ large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the K/sub o/ to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-/spl mu/m 3-V digital CMOS process.

Microwave MEMS-based voltage-controlled oscillators

Abstract: A microwave voltage-controlled oscillator (VCO) based on coupled bonding wire inductors and microelectromechanical system (MEMS)-based variable capacitors for frequency tuning is demonstrated in this paper. The MEMS-based variable capacitors were fabricated in a standard polysilicon surface micromachining technology. The variable capacitors have a nominal capacitance of 1.4 pF and have a Q factor of 23 at 1 GHz and 14 at 2 GHz. The capacitance is variable from 1.4 to 1.9 pF as the tuning voltage is swept from 0 to 5 V. The VCO, fabricated in a 0.5 /spl mu/m CMOS technology, was assembled in a ceramic package where MEMS and CMOS dice were bonded together. The oscillator operates at 2.4 GHz, achieves a phase noise of -122 dBc/Hz at 1 MHz offset from the carrier, and exhibits a tuning range of 3.4%.

Fast-switching frequency synthesizer with a discriminator-aided phase detector

Abstract: A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-/spl mu/m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.

A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology

Abstract: This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW.

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization

Abstract: A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f/sup 3/ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f/sup 3/ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-/spl mu/m BiCMOS process, using only MOS active devices.

Opto-electronic techniques for reducing phase noise in a carrier signal by carrier suppression

Abstract: An oscillator (101) for producing a carrier signal and having an opto-electronic noise suppression module (102) connected between an oscillator output coupler (104) and a control input (164) of the oscillator (101). The opto-electronic noise suppression module (102) includes an opto-electronic unit (110) for producing a first electrical signal (121) indicative of a delayed version of the carrier signal. An electrical interferometer (120) receives the first electrical signal (121) and a second electrical signal indicative of the carrier signal to produce two signals which are combined in a mixer (144) to produce a control signal (152) for the oscillator.

The effect of varactor nonlinearity on the phase noise of completely integrated VCOs

Abstract: This work discusses variations in phase noise over the tuning range of a completely integrated 1.9-GHz differential voltage-controlled oscillator (VCO) fabricated in a 0.5-/spl mu/m bipolar process with 25-GHz f/sub t/. The design had a phase noise of -103 dBc/Hz at 100 kHz offset at the top of the tuning range, but the noise performance degraded to -96 dBc/Hz at 100 kHz at the bottom of the tuning range. It was determined that nonlinearities of the on-chip varactors, which led to excessively high VCO gain at the bottom of the tuning range, were primarily responsible for this degradation in performance. The VCO has a power output of -5 dBm per side. Calculations predict phase noise with only a small error and provide design insight for minimizing this effect. The oscillator core drew 6.4 mA and the output buffer circuitry drew 6 mA, both from a 3.3-V supply.

A 4.5-mW 900-MHz CMOS receiver for wireless paging

Abstract: An ultralow-power 900-MHz receiver implemented on a single CMOS chip is intended for use in FLEX wireless paging. The receiver uses an indirect conversion to zero intermediate frequency (IF) to suppress the flicker noise corner in the second mixer to less than 1 kHz. Various techniques for low-power design, most of them unique to CMOS, are presented, with theoretical support and experimental verifications. The receiver, fabricated in a 0.25-/spl mu/m standard CMOS process, achieves 7.4-dS noise figure at 1.6 kHz with -25-dBm IIP3 on a 1.5 V supply. The voltage-controlled oscillator (VCO) has a phase noise of -98 dBc/Hz at 25 kHz offset. The nominal receiver bias current of 3 mA is higher than the expected 2 mA because of unanticipated losses in coupling capacitors.

A 1.3 GHz low-phase noise fully tunable CMOS LC VCO

Abstract: This paper presents a low-phase noise CMOS LC-VCO, in which a complete compensation of the component spread, due to process variations, can be done. The LC tank is made of a metal-oxide-silicon varactor and a bondwire and a spiral inductor in series. The trade-off between VCO gain variations and phase noise is introduced. The measurements performed on a prototype, powered by a 2-V supply, realized in a digital CMOS process, are presented. The oscillation frequency can be varied in the range 1.1-1.45 G-Hz. The measured phase noise at an offset of 600 kHz from a 1.3-GHz carrier is -119 dBc/Hz, with 6-mA current consumption.

An adaptive PLL tuning system architecture combining high spectral purity and fast settling time

Abstract: An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB.

Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise

Abstract: The proliferation of wireless and mobile products has dramatically increased the number and variety of low power, high performance electronic systems being designed. Noise is an important limiting factor in these systems. The noise generated is often cyclostationary. This type of noise cannot be predicted using SPICE, nor is it well handled by traditional test equipment such as spectrum analyzers or noise figure meters, but it is available from the new RF simulators. The origins and characteristics of cyclostationary noise are described in a way that allows designers to understand the impact of cyclostationarity on their circuits. In particular, cyclostationary noise in time-varying systems (mixers), sampling systems (switched filters and sample/holds), thresholding systems (logic circuitry), and autonomous systems (oscillators) is discussed.

Swath bathymetry using phase difference: theoretical analysis of acoustical measurement precision

Abstract: The phase difference principle is widely applied nowadays to sonar systems used for sea floor bathymetry. The apparent angle of a target point is obtained from the phase difference measured between two close receiving arrays. Here we study the influence of the phase difference estimation errors caused by the physical structure of the backscattered signals. It is shown that, under certain current conditions, beyond the commonly considered effects of additive external noise and baseline decorrelation, the processing may be affected by the shifting footprint effect: this is due to the fact that the two interferometer receivers get simultaneous echo contributions coming from slightly shifted seabed parts, which results in a degradation of the signal coherence and, hence, of the phase difference measurement. This geometrical effect is described analytically and checked with numerical simulations, both for square- and sine-shaped signal envelopes, its relative influence depends on the geometrical configuration and receiver spacing; it may be prevalent in practical cases associated with bathymetric sonars. The cases of square and smooth signal envelopes are both considered. The measurements close to nadir, which are known to be especially difficult with interferometry systems, are addressed in particular.

Phase noise to carrier ratio in LC oscillators

Abstract: An analysis is presented in this contribution to describe the steady-state amplitude of a CMOS LC Colpitts oscillator, as well as its response to small interferences. The problem of signal dependency of noise sources is also addressed. The general conclusions of the analysis are applicable to most LC oscillators. The procedure to perform a general analysis for an arbitrary LC oscillators is outlined. Controlled experiments are used to verify each important conclusion for the Colpitts analysis and implications on design are discussed.

A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture

Abstract: The growing importance of wireless media for voice and data communications is driving a need for higher integration in personal communications transceivers to achieve lower cost, smaller form factor, and lower power dissipation. One approach to this problem is to integrate the RF functionality in low-cost CMOS technology together with the baseband transceiver functions. This in turn requires integration of the frequency synthesizer with enough isolation from supply noise to allow it to coexist with other on-chip transceiver circuitry and still meet the phase noise performance requirements of the application. This differential synthesizer for block-down-convert receivers achieves improved levels of phase noise and supply rejection performance through the use of fully-differential architecture and a wide-bandwidth PLL.

A low-phase-noise CMOS LC oscillator with a ring structure

Abstract: This LC ring oscillator is an architectural experiment to reduce the phase noise of an LC oscillator even further with a ring type structure. An LC oscillator with a special ring type structure performs phase noise filtering and attenuation. To prove the concept, several LC-ring oscillators are fabricated in 0.6 /spl mu/m, single-poly, triple-metal, CMOS. The three-stage LC-ring oscillator has -132 dBc/Hz measured phase noise at 600 kHz offset frequency from a 900 MHz carrier.

A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS

Abstract: A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-/spl mu/m technology occupies 0.09 mm/sup 2/; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV/sub pk/ single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input.

5-GHz SiGe HBT monolithic radio transceiver with tunable filtering

Abstract: A wide-band CDMA-compliant fully integrated 5-GHz radio transceiver was realized in SiGe heterojunction-bipolar-transistor technology with on-chip tunable voltage controlled oscillator (VCO) tracking filters. It allows for wide-band modulation schemes with bandwidth up to 20 MHz. The receiver has a single-ended single-sideband noise figure of 5.9 dB, more than 40 dB on-chip image rejection, an input compression point of -22 dBm, and larger than 70 dB local-oscillator-RF isolation. The phase noise of the on-chip VCO is -100 and -128 dBc/Hz at 100 kHz and 5 MHz offset from the carrier, respectively. The transmitter output compression point is +10 dBm. An image rejection better than 40 dB throughout the VCO tracking range has been demonstrated in the transmitter with all spurious signals 40 dB below the carrier. The differential transceiver draws 125 mA in transmit mode and 45 mA in receive mode from a 3.5-V supply.

Time-variant distortions in OFDM

Abstract: We analyze the degradation of orthogonal frequency division multiplexing (OFDM) signals from time-variant distortions like carrier and sampling frequency offset, Doppler spread and oscillator phase noise. We propose a novel analytical framework in the discrete-time domain based on the FFT demodulation of a single OFDM symbol and unify previous methods with some new results. Exact definitions of the signal-to-subcarrier-interference ratio (SIR) and the effective signal-to-noise ratio (SNR) are given and evaluated for a HIPERLAN/2 system.

Phase noise and additive noise estimation in a qam demodulator

Abstract: A QAM demodulator having a carrier recovery circuit (50) that includes a phase estimation circuit (506) and an additive noise estimation circuit (507) which produces an estimation of the residual phase noise (518) and additive noise (519) viewed by the QAM demodulator. The phase noise estimation (518) is based on the least mean square error (512) between the QAM symbol (509) decided by a symbol decision circuit (508) and the received QAM symbol (504). The additive noise estimation is based on the same error as in the phase noise estimation (518), except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation (519) is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.

Stochastic resonance driven by time-modulated correlated white noise sources

Abstract: We analyze the effects caused by the simultaneous presence of correlated additive and multiplicative noises for stochastic resonance. Besides the standard potential modulation we also consider a time-periodic variation of the correlation between the two noise sources. As a foremost result we find that stochastic resonance, as characterized by the signal-to-noise ratio and the spectral amplification, becomes characteristically broadened. The broadening can be controlled by varying the relative phase shift between the two types of modulation force.

Opto-electronic oscillators having optical resonators

Abstract: Systems and techniques of incorporating an optical resonator (121) in an optical part of a feedback loop (120) in opto-electronic oscillators (100). This optical resonator (121) provides a sufficiently long energy storage time and hence to produce an oscillation of a narrow linewidth and low phase noise. Certain mode matching conditions are required. For example, the mode spacing of the optical resonator (121) is equal to one mode spacing, or a multiplicity of the mode spacing, of an opto-electronic feedback loop that receives a modulated optical signal and to produce an electrical oscillating signal.